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? 2010 microchip technology inc. ds22265a-page 1 mcp444x/446x features ? quad resistor network ? potentiometer or rheostat configuration options ? resistor network resolution - 7-bit: 128 resistors (129 taps) - 8-bit: 256 resistors (257 taps) ?r ab resistances options of: -5k -10k -50k -100k ? zero scale to full scale wiper operation ? low wiper resistance: 75 (typical) ?low tempco: - absolute (rheostat): 50 ppm typical (0c to 70c) - ratiometric (potentiometer): 15 ppm typical ? nonvolatile memory - automatic recall of saved wiper setting - wiperlock? technology - 5 general purpose memory locations ?i 2 c serial interface - 100 khz, 400 khz, and 3.4 mhz support ? serial protocol allows: - high-speed read/write to wiper - read/write to eeprom - write protect to be enabled/disable - wiperlock to be enabled/disabled ? resistor network terminal disconnect feature via terminal control (tcon) register ? reset input pin ? write protect feature: - hardware write protect (wp ) control pin - software write protect (wp) configuration bit ? brown-out reset protection (1.5v typical) ? serial interface inactive current (2.5 ua typical) ? high-voltage tolerant digital inputs: up to 12.5v ? supports split rail applications ? internal weak pull-up on all digital inputs (except scl and sda) ? wide operating voltage: - 2.7v to 5.5v - device characteristics specified - 1.8v to 5.5v - device operation ? wide bandwidth (-3 db) operation: - 2 mhz (typical) for 5.0 k device ? extended temperature range (-40c to +125c) ? package types: 4x4 qfn-20, tssop-20 and tssop-14 package types (top view) mcp44x1 quad potentiometers tssop 1 2 3 4 14 15 17 18 p2a p2w 4x4 qfn 6 7 89 12 13 reset a1 wp p0a p1a p1w sda p3b scl hvc/a0 19 20 p1b p3a p3w v dd mcp44x2 quad rheostat tssop 5 v ss 10 p0w 11 p0b 16 p2b 1 2 3 4 17 18 19 20 reset a1 wp v dd 5 6 7 14 15 16 p0w p0b p0a p1a p1w p1b v ss hvc/a0 sda scl 8 9 10 p3b p3w p3a 12 12 p2w p2a p2b 11 1 2 3 4 11 12 13 14 p0b a1 p0w v dd 5 6 7 8 9 10 p2w p1w p2b p3b p3w p1b v ss hvc/a0 sda scl ep 21 7/8-bit quad i 2 c digital pot with nonvolatile memory
mcp444x/446x ds22265a-page 2 ? 2010 microchip technology inc. device block diagram device features device # of pots wiper configuration control memory type wiperlock technology por wiper setting resistance (typical) # of taps v dd operating range (2) r ab options (k ) wiper - r w ( ) mcp4431 (3) 4 potentiometer (1) i 2 c ram no mid-scale 5.0, 10.0, 50.0, 100.0 75 129 1.8v to 5.5v mcp4432 (3) 4 rheostat i 2 c ram no mid-scale 5.0, 10.0, 50.0, 100.0 75 129 1.8v to 5.5v mcp4441 4 potentiometer (1) i 2 c ee yes nv wiper 5.0, 10.0, 50.0, 100.0 75 129 2.7v to 5.5v mcp4442 4 rheostat i 2 c ee yes nv wiper 5.0, 10.0, 50.0, 100.0 75 129 2.7v to 5.5v mcp4451 (3) 4 potentiometer (1) i 2 c ram no mid-scale 5.0, 10.0, 50.0, 100.0 75 257 1.8v to 5.5v mcp4452 (3) 4 rheostat i 2 c ram no mid-scale 5.0, 10.0, 50.0, 100.0 75 257 1.8v to 5.5v mcp4461 4 potentiometer (1) i 2 c ee yes nv wiper 5.0, 10.0, 50.0, 100.0 75 257 2.7v to 5.5v mcp4462 4 rheostat i 2 c ee yes nv wiper 5.0, 10.0, 50.0, 100.0 75 257 2.7v to 5.5v note 1: floating either terminal (a or b) allows the device to be used as a rheostat (variable resistor). 2: analog characteristics only tested from 2.7v to 5.5v unless otherwise noted. 3: please check microchip web site for device release and availability. power-up/ brown-out control v dd v ss i 2 c serial interface module & control logic (wiperlock? technology) resistor network 0 (pot 0) wiper 0 & tcon0 register resistor network 1 (pot 1) wiper 1 & tcon0 register hvc/a0 scl sda a1 wp reset memory (16x9) wiper0 (v & nv) wiper1 (v & nv) tcon0 status data eeprom (5 x 9-bits) p0a p0w p0b p1a p1w p1b resistor network 2 (pot 2) wiper 2 & tcon1 register p2a p2w p2b resistor network 3 (pot 3) wiper 3 & tcon1 register p3a p3w p3b wiper2 (v & nv) wiper3 (v & nv) tcon1
? 2010 microchip technology inc. ds22265a-page 3 mcp444x/446x 1.0 electrical characteristics absolute maximum ratings ? voltage on v dd with respect to v ss ................ -0.6v to +7.0v voltage on hvc/a0, a1, scl, sda, wp , and reset with respect to v ss ................................... -0.6v to 12.5v voltage on all other pins (pxa, pxw, and pxb) with respect to v ss ......................................... -0.3v to v dd + 0.3v input clamp current, i ik (v i < 0, v i > v dd , v i > v pp on hv pins) ......................20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ..................................................20 ma maximum output current sunk by any output pin ......................................................................................25 ma maximum output current sourced by any output pin ed ......................................................................................25 ma maximum current out of v ss pin .................................100 ma maximum current into v dd pin ....................................100 ma maximum current into p x a, p x w & p x b pins ............2.5 ma storage temperature ....................................-65c to +150c ambient temperature with power applied ..................................................................... -40c to +125c package power dissipation (t a = +50c, t j = +150c) tssop-14....................................................... 1000 mw tssop-20....................................................... 1110 mw qfn-20 (4x4) .................................................. 2320 mw soldering temperature of leads (10 seconds) ............. +300c esd protection on all pins ................................... 4 kv (hbm), .......................................................................... 300v (mm) maximum junction temperature (t j ) ......................... +150c ? notice: stresses above those listed under ?maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this s pecification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
mcp444x/446x ds22265a-page 4 ? 2010 microchip technology inc. ac/dc characteristics dc characteristics standard operating conditions (unless otherwise specified) operating temperature ?40c t a +125c (extended) all parameters apply across the specified operating ranges unless noted. v dd = +2.7v to 5.5v, 5 k , 10 k , 50 k , 100 k devices. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym min typ max units conditions supply voltage v dd 2.7 ? 5.5 v 1.8 ? 2.7 v serial interface only. hvc/a0, sda, scl, a1, wp , reset pin voltage range v hv v ss ?12.5v vv dd 4.5v the hvc/a0 pin will be at one of three input levels (v il , v ih or v ihh ). ( note 6 ) v ss ?v dd + 8.0v vv dd < 4.5v v dd start voltage to ensure wiper reset v bor ? ? 1.65 v ram retention voltage (v ram ) < v bor v dd rise rate to ensure power-on reset v ddrr ( note 9 )v/ms delay after device exits the reset state (v dd > v bor ) t bord ?1020s supply current ( note 10 ) i dd ? ? 600 a serial interface active, hvc/a0 = v ih (or v il ) ( note 11 ) write all 0 ?s to volatile wiper 0 v dd = 5.5v, f scl @ 3.4 mhz ? ? 250 a serial interface active, hvc/a0 = v ih (or v il ) ( note 11 ) write all 0 ?s to volatile wiper 0 v dd = 5.5v, f scl @ 100 khz ? ? 575 a ee write current (write cycle) (nonvolatile device only), v dd = 5.5v, f scl = 400 khz, write all 0 ?s to nonvolatile wiper 0 scl = v il or v ih ? 2.5 5 a serial interface inactive, (stop condition, scl = sda = v ih ), wiper = 0 v dd = 5.5v, hvc/a0 = v ih note 1: resistance is defined as the resistance between terminal a to terminal b. 2: inl and dnl are measured at v w with v a = v dd and v b = v ss . 3: mcp44x1 only. 4: mcp44x2 only, includes v wzse and v wfse . 5: resistor terminals a, w and b?s polarity with respect to each other is not restricted. 6: this specification by design. 7: non-linearity is affected by wiper resistance (r w ), which changes significantly over voltage and temperature. 8: the mcp44x1 is externally connected to match the configurations of the mcp44x2 , and then tested. 9: por/bor is not rate dependent. 10: supply current is independent of current through the resistor network. 11: when hvc/a0 = v ihh , the i dd current is less due to current into the hvc/a0 pin. see i pu specification.
? 2010 microchip technology inc. ds22265a-page 5 mcp444x/446x resistance ( 20%) r ab 4.0 5 6.0 k -502 devices ( note 1 ) 8.0 10 12.0 k -103 devices ( note 1 ) 40.0 50 60.0 k -503 devices ( note 1 ) 80.0 100 120.0 k -104 devices ( note 1 ) resolution n 257 taps 8-bit no missing codes 129 taps 7-bit no missing codes step resistance r s ?r ab / (256) ? 8-bit note 6 ?r ab / (128) ? 7-bit note 6 nominal resistance match (| r abwc - r abmean |) / r abmean ? 0.2 1.50 % 5 k mcp44x1 devices only ? 0.2 1.25 % 10 k ?0.21.0%50k ? 0.2 1.0 % 100 k (| r bwwc - r bwmean |) / r bwmean ?0.251.75%5k code = full scale ?0.251.50%10k ?0.251.25%50k ? 0.25 1.25 % 100 k wiper resistance ( note 3 , note 4 ) r w ? 75 160 v dd = 5.5 v, i w = 2.0 ma, code = 00h ? 75 300 v dd = 2.7 v, i w = 2.0 ma, code = 00h nominal resistance te m p c o r ab / t?50?ppm/ct a = -20c to +70c ?100?ppm/ct a = -40c to +85c ?150?ppm/ct a = -40c to +125c ratiometeric te m p c o v wb / t ? 15 ? ppm/c code = midscale (80h or 40h) resistance tracking r track section 2.0 ppm/c see typical performance curves ac/dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature ?40c t a +125c (extended) all parameters apply across the specified operating ranges unless noted. v dd = +2.7v to 5.5v, 5 k , 10 k , 50 k , 100 k devices. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym min typ max units conditions note 1: resistance is defined as the resistance between terminal a to terminal b. 2: inl and dnl are measured at v w with v a = v dd and v b = v ss . 3: mcp44x1 only. 4: mcp44x2 only, includes v wzse and v wfse . 5: resistor terminals a, w and b?s polarity with respect to each other is not restricted. 6: this specification by design. 7: non-linearity is affected by wiper resistance (r w ), which changes significantly over voltage and temperature. 8: the mcp44x1 is externally connected to match the configurations of the mcp44x2 , and then tested. 9: por/bor is not rate dependent. 10: supply current is independent of current through the resistor network. 11: when hvc/a0 = v ihh , the i dd current is less due to current into the hvc/a0 pin. see i pu specification.
mcp444x/446x ds22265a-page 6 ? 2010 microchip technology inc. resistor terminal input voltage range (terminals a, b and w) v a, v w, v b vss ? v dd v note 5 , note 6 maximum current through a, w or b ( note 6 ) i w ? ? 2.5 ma terminal a i aw , w = full scale (fs) ? ? 2.5 ma terminal b i bw , w = zero scale (zs) ? ? 2.5 ma terminal w i aw (w = fs) or i bw (w = zs) maximum r ab current (i ab ) ( note 6 ) i ab ??1.38mav b = 0v, v a = 5.5v, r ab(min) = 4000 ? ? 0.688 ma v b = 0v, v a = 5.5v, r ab(min) = 8000 ? ? 0.138 ma v b = 0v, v a = 5.5v, r ab(min) = 40000 ? ? 0.069 ma v b = 0v, v a = 5.5v, r ab(min) = 80000 leakage current into a, w or b i wl ?100?na mcp44x1 pxa = pxw = pxb = v ss ?100?na mcp44x2 pxb = pxw = v ss ? 100 ? na terminals disconnected (r0a = r0w = r0b = 0; r1a = r1w = r1b = 0; r2a = r2w = r2b = 0; r3a = r3w = r3b = 0) ac/dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature ?40c t a +125c (extended) all parameters apply across the specified operating ranges unless noted. v dd = +2.7v to 5.5v, 5 k , 10 k , 50 k , 100 k devices. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym min typ max units conditions note 1: resistance is defined as the resistance between terminal a to terminal b. 2: inl and dnl are measured at v w with v a = v dd and v b = v ss . 3: mcp44x1 only. 4: mcp44x2 only, includes v wzse and v wfse . 5: resistor terminals a, w and b?s polarity with respect to each other is not restricted. 6: this specification by design. 7: non-linearity is affected by wiper resistance (r w ), which changes significantly over voltage and temperature. 8: the mcp44x1 is externally connected to match the configurations of the mcp44x2 , and then tested. 9: por/bor is not rate dependent. 10: supply current is independent of current through the resistor network. 11: when hvc/a0 = v ihh , the i dd current is less due to current into the hvc/a0 pin. see i pu specification.
? 2010 microchip technology inc. ds22265a-page 7 mcp444x/446x full scale error ( mcp44x1 only) (8-bit code = 100h, 7-bit code = 80h) v wfse -6.0 -0.1 ? lsb 5 k 8-bit 3.0v v dd 5.5v -4.0 -0.1 ? lsb 7-bit 3.0v v dd 5.5v -3.5 -0.1 ? lsb 10 k 8-bit 3.0v v dd 5.5v -2.0 -0.1 ? lsb 7-bit 3.0v v dd 5.5v -0.8 -0.1 ? lsb 50 k 8-bit 3.0v v dd 5.5v -0.5 -0.1 ? lsb 7-bit 3.0v v dd 5.5v -0.5 -0.1 ? lsb 100 k 8-bit 3.0v v dd 5.5v -0.5 -0.1 ? lsb 7-bit 3.0v v dd 5.5v zero scale error ( mcp44x1 only) (8-bit code = 00h, 7-bit code = 00h) v wzse ?+0.1+6.0lsb5k 8-bit 3.0v v dd 5.5v ? +0.1 +3.0 lsb 7-bit 3.0v v dd 5.5v ? +0.1 +3.5 lsb 10 k 8-bit 3.0v v dd 5.5v ? +0.1 +2.0 lsb 7-bit 3.0v v dd 5.5v ? +0.1 +0.8 lsb 50 k 8-bit 3.0v v dd 5.5v ? +0.1 +0.5 lsb 7-bit 3.0v v dd 5.5v ? +0.1 +0.5 lsb 100 k 8-bit 3.0v v dd 5.5v ? +0.1 +0.5 lsb 7-bit 3.0v v dd 5.5v potentiometer integral non-linearity inl -1 0.5 +1 lsb 8-bit 3.0v v dd 5.5v mcp44x1 devices only ( note 2 ) -0.5 0.25 +0.5 lsb 7-bit potentiometer differential non- linearity dnl -0.5 0.25 +0.5 lsb 8-bit 3.0v v dd 5.5v mcp44x1 devices only ( note 2 ) -0.25 0.125 +0.25 lsb 7-bit bandwidth -3 db (see figure 2-72 , load = 30 pf) bw ? 2 ? mhz 5 k 8-bit code = 80h ? 2 ? mhz 7-bit code = 40h ?1?mhz10k 8-bit code = 80h ? 1 ? mhz 7-bit code = 40h ?200?khz50k 8-bit code = 80h ? 200 ? khz 7-bit code = 40h ? 100 ? khz 100 k 8-bit code = 80h ? 100 ? khz 7-bit code = 40h ac/dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature ?40c t a +125c (extended) all parameters apply across the specified operating ranges unless noted. v dd = +2.7v to 5.5v, 5 k , 10 k , 50 k , 100 k devices. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym min typ max units conditions note 1: resistance is defined as the resistance between terminal a to terminal b. 2: inl and dnl are measured at v w with v a = v dd and v b = v ss . 3: mcp44x1 only. 4: mcp44x2 only, includes v wzse and v wfse . 5: resistor terminals a, w and b?s polarity with respect to each other is not restricted. 6: this specification by design. 7: non-linearity is affected by wiper resistance (r w ), which changes significantly over voltage and temperature. 8: the mcp44x1 is externally connected to match the configurations of the mcp44x2 , and then tested. 9: por/bor is not rate dependent. 10: supply current is independent of current through the resistor network. 11: when hvc/a0 = v ihh , the i dd current is less due to current into the hvc/a0 pin. see i pu specification.
mcp444x/446x ds22265a-page 8 ? 2010 microchip technology inc. rheostat integral non-linearity mcp44x1 ( note 4 , note 8 ) mcp44x2 devices only ( note 4 ) r-inl -1.5 0.5 +1.5 lsb 5 k 8-bit 5.5v, i w = 900 a -8.25 +4.5 +8.25 lsb 3.0v, i w = 480 a ( note 7 ) -1.125 0.5 +1.125 lsb 7-bit 5.5v, i w = 900 a -6.0 +4.5 +6.0 lsb 3.0v, i w = 480 a ( note 7 ) -1.5 0.5 +1.5 lsb 10 k 8-bit 5.5v, i w = 450 a -5.5 +2.5 +5.5 lsb 3.0v, i w = 240 a ( note 7 ) -1.125 0.5 +1.125 lsb 7-bit 5.5v, i w = 450 a -4.0 +2.5 +4.0 lsb 3.0v, i w = 240 a ( note 7 ) -1.5 0.5 +1.5 lsb 50 k 8-bit 5.5v, i w = 90 a -2.0 +1 +2.0 lsb 3.0v, i w = 48 a ( note 7 ) -1.125 0.5 +1.125 lsb 7-bit 5.5v, i w = 90 a -1.5 +1 +1.5 lsb 3.0v, i w = 48 a ( note 7 ) -1.0 0.5 +1.0 lsb 100 k 8-bit 5.5v, i w = 45 a -1.5 +0.25 +1.5 lsb 3.0v, i w = 24 a ( note 7 ) -0.8 0.5 +0.8 lsb 7-bit 5.5v, i w = 45 a -1.125 +0.25 +1.125 lsb 3.0v, i w = 24 a ( note 7 ) ac/dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature ?40c t a +125c (extended) all parameters apply across the specified operating ranges unless noted. v dd = +2.7v to 5.5v, 5 k , 10 k , 50 k , 100 k devices. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym min typ max units conditions note 1: resistance is defined as the resistance between terminal a to terminal b. 2: inl and dnl are measured at v w with v a = v dd and v b = v ss . 3: mcp44x1 only. 4: mcp44x2 only, includes v wzse and v wfse . 5: resistor terminals a, w and b?s polarity with respect to each other is not restricted. 6: this specification by design. 7: non-linearity is affected by wiper resistance (r w ), which changes significantly over voltage and temperature. 8: the mcp44x1 is externally connected to match the configurations of the mcp44x2 , and then tested. 9: por/bor is not rate dependent. 10: supply current is independent of current through the resistor network. 11: when hvc/a0 = v ihh , the i dd current is less due to current into the hvc/a0 pin. see i pu specification.
? 2010 microchip technology inc. ds22265a-page 9 mcp444x/446x rheostat differential non- linearity mcp44x1 ( note 4 , note 8 ) mcp44x2 devices only ( note 4 ) r-dnl -0.5 0.25 +0.5 lsb 5 k 8-bit 5.5v, i w = 900 a -1.0 +0.5 +1.0 lsb 3.0v, i w = 480 a ( note 7 ) -0.375 0.25 +0.375 lsb 7-bit 5.5v, i w = 900 a -0.75 +0.5 +0.75 lsb 3.0v, i w = 480 a ( note 7 ) -0.5 0.25 +0.5 lsb 10 k 8-bit 5.5v, i w = 450 a -1.0 +0.25 +1.0 lsb 3.0v, i w = 240 a ( note 7 ) -0.375 0.25 +0.375 lsb 7-bit 5.5v, i w = 450 a -0.75 +0.5 +0.75 lsb 3.0v, i w = 240 a ( note 7 ) -0.5 0.25 +0.5 lsb 50 k 8-bit 5.5v, i w = 90 a -0.5 0.25 +0.5 lsb 3.0v, i w = 48 a ( note 7 ) -0.375 0.25 +0.375 lsb 7-bit 5.5v, i w = 90 a -0.375 0.25 +0.375 lsb 3.0v, i w = 48 a ( note 7 ) -0.5 0.25 +0.5 lsb 100 k 8-bit 5.5v, i w = 45 a -0.5 0.25 +0.5 lsb 3.0v, i w = 24 a ( note 7 ) -0.375 0.25 +0.375 lsb 7-bit 5.5v, i w = 45 a -0.375 0.25 +0.375 lsb 3.0v, i w = 24 a ( note 7 ) capacitance (p a )c aw ? 75 ? pf f =1 mhz, code = full scale capacitance (p w )c w ? 120 ? pf f =1 mhz, code = full scale capacitance (p b )c bw ? 75 ? pf f =1 mhz, code = full scale ac/dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature ?40c t a +125c (extended) all parameters apply across the specified operating ranges unless noted. v dd = +2.7v to 5.5v, 5 k , 10 k , 50 k , 100 k devices. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym min typ max units conditions note 1: resistance is defined as the resistance between terminal a to terminal b. 2: inl and dnl are measured at v w with v a = v dd and v b = v ss . 3: mcp44x1 only. 4: mcp44x2 only, includes v wzse and v wfse . 5: resistor terminals a, w and b?s polarity with respect to each other is not restricted. 6: this specification by design. 7: non-linearity is affected by wiper resistance (r w ), which changes significantly over voltage and temperature. 8: the mcp44x1 is externally connected to match the configurations of the mcp44x2 , and then tested. 9: por/bor is not rate dependent. 10: supply current is independent of current through the resistor network. 11: when hvc/a0 = v ihh , the i dd current is less due to current into the hvc/a0 pin. see i pu specification.
mcp444x/446x ds22265a-page 10 ? 2010 microchip technology inc. digital inputs/outputs (hvc/a0, a1, sda, scl, wp , reset ) schmitt trigger high input threshold v ih 0.45 v dd ? ? v all inputs except sda and scl 2.7v v dd 5.5v (allows 2.7v digital v dd with 5v analog v dd ) 0.5 v dd ?? v 1.8v v dd 2.7v 0.7 v dd ?v max v sda and scl 100 khz 0.7 v dd ?v max v400khz 0.7 v dd ?v max v1.7mhz 0.7 v dd ?v max v3.4mhz schmitt trigger low input threshold v il ? ? 0.2v dd v all inputs except sda and scl -0.5 ? 0.3v dd v sda and scl 100 khz -0.5 ? 0.3v dd v400khz -0.5 ? 0.3v dd v1.7mhz -0.5 ? 0.3v dd v3.4mhz hysteresis of schmitt trigger inputs v hys ?0.1v dd ? v all inputs except sda and scl n.a. ? ? v sda and scl 100 khz v dd < 2.0v n.a. ? ? v v dd 2.0v 0.1 v dd ?? v 400 khz v dd < 2.0v 0.05 v dd ?? v v dd 2.0v 0.1 v dd ?? v 1.7mhz 0.1 v dd ?? v 3.4mhz high voltage input entry voltage v ihhen 9.0 ? 12.5 ( note 6 ) v threshold for wiperlock technology high voltage input exit voltage v ihhex ??v dd + 0.8v ( note 6 ) v high voltage limit v max ??12.5 ( note 6 ) v pin can tolerate v max or less. output low voltage (sda) v ol v ss ?0.2v dd vv dd < 2.0v, i ol = 1 ma, v ss ?0.4 vv dd 2.0v, i ol = 3 ma ac/dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature ?40c t a +125c (extended) all parameters apply across the specified operating ranges unless noted. v dd = +2.7v to 5.5v, 5 k , 10 k , 50 k , 100 k devices. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym min typ max units conditions note 1: resistance is defined as the resistance between terminal a to terminal b. 2: inl and dnl are measured at v w with v a = v dd and v b = v ss . 3: mcp44x1 only. 4: mcp44x2 only, includes v wzse and v wfse . 5: resistor terminals a, w and b?s polarity with respect to each other is not restricted. 6: this specification by design. 7: non-linearity is affected by wiper resistance (r w ), which changes significantly over voltage and temperature. 8: the mcp44x1 is externally connected to match the configurations of the mcp44x2 , and then tested. 9: por/bor is not rate dependent. 10: supply current is independent of current through the resistor network. 11: when hvc/a0 = v ihh , the i dd current is less due to current into the hvc/a0 pin. see i pu specification.
? 2010 microchip technology inc. ds22265a-page 11 mcp444x/446x weak pull-up current i pu ? ? 1.75 ma internal v dd pull-up, v ihh pull-down, v dd = 5.5v, v hvc = 12.5v ? 170 ? a hvc pin, v dd = 5.5v, v hvc = 3v hvc pull-up / pull-down resistance r hvc ?16?k v dd = 5.5v, v hvc = 3v reset pull-up resistance r reset ?16?k v dd = 5.5v, v reset = 0v input leakage current i il -1 ? 1 a v in = v dd (all pins) and v in = v ss (all pins except reset ) pin capacitance c in , c out ?10?pff c = 20 mhz ram (wiper, tcon) value value range n 0h ? 1ffh hex 8-bit device 0h ? 1ffh hex 7-bit device tcon por/bor setting 1ff hex all terminals connected eeprom endurance e ndurance ?1m?cycles eeprom range n 0h ? 1ffh hex initial nv wiper por/bor setting n 080h hex 8-bit wiperlock technology = off 040h hex 7-bit wiperlock technology = off initial eeprom por/bor setting n 000h hex eeprom programming write cycle time t wc ?310ms power requirements power supply sensitivity ( mcp44x1 ) pss ? 0.0015 0.0035 %/% 8-bit v dd = 2.7v to 5.5v, v a = 2.7v, code = 80h ? 0.0015 0.0035 %/% 7-bit v dd = 2.7v to 5.5v, v a = 2.7v, code = 40h ac/dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature ?40c t a +125c (extended) all parameters apply across the specified operating ranges unless noted. v dd = +2.7v to 5.5v, 5 k , 10 k , 50 k , 100 k devices. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym min typ max units conditions note 1: resistance is defined as the resistance between terminal a to terminal b. 2: inl and dnl are measured at v w with v a = v dd and v b = v ss . 3: mcp44x1 only. 4: mcp44x2 only, includes v wzse and v wfse . 5: resistor terminals a, w and b?s polarity with respect to each other is not restricted. 6: this specification by design. 7: non-linearity is affected by wiper resistance (r w ), which changes significantly over voltage and temperature. 8: the mcp44x1 is externally connected to match the configurations of the mcp44x2 , and then tested. 9: por/bor is not rate dependent. 10: supply current is independent of current through the resistor network. 11: when hvc/a0 = v ihh , the i dd current is less due to current into the hvc/a0 pin. see i pu specification.
mcp444x/446x ds22265a-page 12 ? 2010 microchip technology inc. 1.1 i 2 c mode timing waveforms and requirements figure 1-1: reset waveforms. table 1-1: reset timing timing characteristics standard operating conditions (unless otherwise specified) operating temperature ?40c t a +125c (extended) all parameters apply across the specified operating ranges unless noted. v dd = +2.7v to 5.5v, 5 k , 10 k , 50 k , 100 k devices. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym min typ max units conditions reset pulse width t rst 50 ? ? ns reset rising edge normal mode (wiper driving and i 2 c interface operational) t rstd ??20ns reset sda t rst t rstd wx scl v ih v ih
? 2010 microchip technology inc. ds22265a-page 13 mcp444x/446x figure 1-2: i 2 c bus start/stop bits timing waveforms. table 1-2: i 2 c bus start/stop bits requirements i 2 c ac characteristics standard operating conditions (unless otherwise specified) operating temperature ?40 c t a +125 c (extended) operating voltage v dd range is described in ac/dc characteristics param. no. symbol characteristic min max units conditions f scl standard mode 0 100 khz c b = 400 pf, 1.8v - 5.5v fast mode 0 400 khz c b = 400 pf, 2.7v - 5.5v high-speed 1.7 0 1.7 mhz c b = 400 pf, 4.5v - 5.5v high-speed 3.4 0 3.4 mhz c b = 100 pf, 4.5v - 5.5v d102 cb bus capacitive loading 100 khz mode ? 400 pf 400 khz mode ? 400 pf 1.7 mhz mode ? 400 pf 3.4 mhz mode ? 100 pf 90 t su : sta start condition 100 khz mode 4700 ? ns only relevant for repeated start condition setup time 400 khz mode 600 ? ns 1.7 mhz mode 160 ? ns 3.4 mhz mode 160 ? ns 91 t hd : sta start condition 100 khz mode 4000 ? ns after this period the first clock pulse is generated hold time 400 khz mode 600 ? ns 1.7 mhz mode 160 ? ns 3.4 mhz mode 160 ? ns 92 t su : sto stop condition 100 khz mode 4000 ? ns setup time 400 khz mode 600 ? ns 1.7 mhz mode 160 ? ns 3.4 mhz mode 160 ? ns 93 t hd : sto stop condition 100 khz mode 4000 ? ns hold time 400 khz mode 600 ? ns 1.7 mhz mode 160 ? ns 3.4 mhz mode 160 ? ns 94 t hvcsu hvc to scl setup time 25 ? us high voltage commands 95 t hvchd scl to hvc hold time 25 ? us high voltage commands 91 93 scl sda start condition stop condition 90 92 hvc/a0 v ih v ihh v ih or v il or v il 94 95
mcp444x/446x ds22265a-page 14 ? 2010 microchip technology inc. figure 1-3: i 2 c bus data timing. 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out table 1-3: i 2 c bus data requirements (slave mode) i 2 c ac characteristics standard operating conditions (unless otherwise specified) operating temperature ?40 c t a +125 c (extended) operating voltage v dd range is described in ac/dc characteristics param. no. sym characteristic min max units conditions 100 t high clock high time 100 khz mode 4000 ? ns 1.8v-5.5v 400 khz mode 600 ? ns 2.7v-5.5v 1.7 mhz mode 120 ns 4.5v-5.5v 3.4 mhz mode 60 ? ns 4.5v-5.5v 101 t low clock low time 100 khz mode 4700 ? ns 1.8v-5.5v 400 khz mode 1300 ? ns 2.7v-5.5v 1.7 mhz mode 320 ns 4.5v-5.5v 3.4 mhz mode 160 ? ns 4.5v-5.5v note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast-mode (400 khz) i 2 c-bus device can be used in a standard-mode (100 khz) i 2 c-bus system, but the requirement t su;dat 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max.+t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c bus specification) before the scl line is released. 3: the mcp44x1/mcp44x2 device must provide a data hold time to bridge the undefined part between v ih and v il of the falling edge of the scl signal. this specification is not a part of the i 2 c specification, but must be tested in order to ensure that the output data will meet the setup and hold specifications for the receiving device. 4: use cb in pf for the calculations. 5: not tested. 6: a master transmitter must provide a delay to ensure that difference between sda and scl fall times do not unintentionally create a start or stop condition. 7: ensured by the t aa 3.4 mhz specification test.
? 2010 microchip technology inc. ds22265a-page 15 mcp444x/446x 102a (5) t rscl scl rise time 100 khz mode ? 1000 ns cb is specified to be from 10 to 400 pf (100 pf maxi- mum for 3.4 mhz mode) 400 khz mode 20 + 0.1cb 300 ns 1.7 mhz mode 20 80 ns 1.7 mhz mode 20 160 ns after a repeated start con- dition or an acknowledge bit 3.4 mhz mode 10 40 ns 3.4 mhz mode 10 80 ns after a repeated start condition or an acknowl- edge bit 102b (5) t rsda sda rise time 100 khz mode ? 1000 ns cb is specified to be from 10 to 400 pf (100 pf max for 3.4 mhz mode) 400 khz mode 20 + 0.1cb 300 ns 1.7 mhz mode 20 160 ns 3.4 mhz mode 10 80 ns 103a (5) t fscl scl fall time 100 khz mode ? 300 ns cb is specified to be from 10 to 400 pf (100 pf max for 3.4 mhz mode) 400 khz mode 20 + 0.1cb 300 ns 1.7 mhz mode 20 80 ns 3.4 mhz mode 10 40 ns 103b (5) t fsda sda fall time 100 khz mode ? 300 ns cb is specified to be from 10 to 400 pf (100 pf max for 3.4 mhz mode) 400 khz mode 20 + 0.1cb (4) 300 ns 1.7 mhz mode 20 160 ns 3.4 mhz mode 10 80 ns 106 t hd:dat data input hold time 100 khz mode 0 ? ns 1.8v-5.5v, note 6 400 khz mode 0 ? ns 2.7v-5.5v, note 6 1.7 mhz mode 0 ? ns 4.5v-5.5v, note 6 3.4 mhz mode 0 ? ns 4.5v-5.5v, note 6 table 1-3: i 2 c bus data requirements (slave mode) (continued) i 2 c ac characteristics standard operating conditions (unless otherwise specified) operating temperature ?40 c t a +125 c (extended) operating voltage v dd range is described in ac/dc characteristics param. no. sym characteristic min max units conditions note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast-mode (400 khz) i 2 c-bus device can be used in a standard-mode (100 khz) i 2 c-bus system, but the requirement t su;dat 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max.+t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c bus specification) before the scl line is released. 3: the mcp44x1/mcp44x2 device must provide a data hold time to bridge the undefined part between v ih and v il of the falling edge of the scl signal. this specification is not a part of the i 2 c specification, but must be tested in order to ensure that the output data will meet the setup and hold specifications for the receiving device. 4: use cb in pf for the calculations. 5: not tested. 6: a master transmitter must provide a delay to ensure that difference between sda and scl fall times do not unintentionally create a start or stop condition. 7: ensured by the t aa 3.4 mhz specification test.
mcp444x/446x ds22265a-page 16 ? 2010 microchip technology inc. 107 t su:dat data input setup time 100 khz mode 250 ? ns note 2 400 khz mode 100 ? ns 1.7 mhz mode 10 ? ns 3.4 mhz mode 10 ? ns 109 t aa output valid from clock 100 khz mode ? 3450 ns note 1 400 khz mode ? 900 ns 1.7 mhz mode ? 150 ns cb = 100 pf, note 1 , note 7 ? 310 ns cb = 400 pf, note 1 , note 5 3.4 mhz mode ? 150 ns cb = 100 pf, note 1 110 t buf bus free time 100 khz mode 4700 ? ns time the bus must be free before a new transmission can start 400 khz mode 1300 ? ns 1.7 mhz mode n.a. ? ns 3.4 mhz mode n.a. ? ns t sp input filter spike suppression (sda and scl) 100 khz mode ? 50 ns philips spec states n.a. 400 khz mode ? 50 ns 1.7 mhz mode ? 10 ns spike suppression 3.4 mhz mode ? 10 ns spike suppression table 1-3: i 2 c bus data requirements (slave mode) (continued) i 2 c ac characteristics standard operating conditions (unless otherwise specified) operating temperature ?40 c t a +125 c (extended) operating voltage v dd range is described in ac/dc characteristics param. no. sym characteristic min max units conditions note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast-mode (400 khz) i 2 c-bus device can be used in a standard-mode (100 khz) i 2 c-bus system, but the requirement t su;dat 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max.+t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c bus specification) before the scl line is released. 3: the mcp44x1/mcp44x2 device must provide a data hold time to bridge the undefined part between v ih and v il of the falling edge of the scl signal. this specification is not a part of the i 2 c specification, but must be tested in order to ensure that the output data will meet the setup and hold specifications for the receiving device. 4: use cb in pf for the calculations. 5: not tested. 6: a master transmitter must provide a delay to ensure that difference between sda and scl fall times do not unintentionally create a start or stop condition. 7: ensured by the t aa 3.4 mhz specification test.
? 2010 microchip technology inc. ds22265a-page 17 mcp444x/446x temperature characteristics electrical specifications: unless otherwise indicated, v dd = +2.7v to +5.5v, v ss = gnd. parameters sym min typ max units conditions temperature ranges specified temperature range t a -40 ? +125 c operating temperature range t a -40 ? +125 c storage temperature range t a -65 ? +150 c thermal package resistances thermal resistance, 14l-tssop ja ?100?c/w thermal resistance, 20l-qfn ja ?43?c/w thermal resistance, 20l-tssop ja ?90?c/w
mcp444x/446x ds22265a-page 18 ? 2010 microchip technology inc. notes:
? 2010 microchip technology inc. ds22265a-page 19 mcp444x/446x 2.0 typical performance curves note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-1: device current (i dd ) vs. i 2 c frequency (f scl ) and ambient temperature (v dd = 2.7v and 5.5v). figure 2-2: device current (i shdn ) and v dd . (hvc/a0 = v dd ) vs. ambient temperature. figure 2-3: write current (i write ) vs. ambient temperature and v dd . figure 2-4: hvc/a0 pull-up/pull-down resistance (r hvc ) and current (i hvc ) vs. hvc/ a0 input voltage (v hvc ) (v dd = 5.5v). figure 2-5: hvc/a0 high input entry/ exit threshold vs. ambient temperature and v dd . note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 0 50 100 150 200 250 300 350 400 450 500 550 -40 0 40 80 120 temperature (c) i dd (a) 3.4mhz, 5.5v 3.4mhz, 4.5v 1.7mhz, 5.5v 1.7mhz, 4.5v 400khz, 5.5v 400khz, 2.7v 100khz, 5.5v 100khz, 2.7v 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -40 0 40 80 120 ambient temperature (c) standby current (i shdn ) (a) 5.5v 2.7v 0 100 200 300 400 500 -40 0 40 80 120 ambient temperature (c) ee write current (i write ) (a) 5.5v 2.7v 0 50 100 150 200 250 2345678910 v hvc (v) r hvc (kohms) -1000 -800 -600 -400 -200 0 200 400 600 800 1000 i hvc r hvc i hvc (a) 0.0 2.0 4.0 6.0 8.0 10.0 12.0 -40 0 40 80 120 ambient temperature (c) hvc/a0 threshold (v) 2.7v entry 2.7v exit 5.5v entry 5.5v exit
mcp444x/446x ds22265a-page 20 ? 2010 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-6: 5k pot mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 5.5v). figure 2-7: 5k pot mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 3.0v). figure 2-8: 5k rheo mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 5.5v). figure 2-9: 5k rheo mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 3.0v). 20 40 60 80 100 120 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 60 100 140 180 220 260 300 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl -40c 25c 85c r w 125c 20 40 60 80 100 120 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -1.25 -0.75 -0.25 0.25 0.75 1.25 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 60 100 140 180 220 260 300 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -2 0 2 4 6 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dn l inl dnl r w -40c 25c 85c 125c
? 2010 microchip technology inc. ds22265a-page 21 mcp444x/446x note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-10: 5k ? nominal resistance (r ab ) ( ) vs. ambient temperature and v dd . figure 2-11: 5k ? r wb ( ) vs. wiper setting and ambient temperature (v dd = 5.5v, i w = 190 a). figure 2-12: 5k ? r wb ( ) vs. wiper setting and ambient temperature (v dd = 3.0v, i w = 190 a). 5050 5100 5150 5200 5250 5300 -40 0 40 80 120 ambient temperature (c) nominal resistance (r ab ) (ohms) 2.7v 5.5v 0 1000 2000 3000 4000 5000 6000 0 32 64 96 128 160 192 224 256 wiper code resistance () -40c +25c +85c +125c 0 1000 2000 3000 4000 5000 6000 0 32 64 96 128 160 192 224 256 wiper code resistance () -40c +25c +85c +125c
mcp444x/446x ds22265a-page 22 ? 2010 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-13: 5k ? worst case r bw from average r bw (r bw0 -r bw3 ) error (%) vs. wiper setting and temperature (v dd = 5.5v, i w = 190 a). figure 2-14: 5k ? worst case r bw from average r bw (r bw0 -r bw3 ) error (%) vs. wiper setting and temperature (v dd = 3.0v, i w = 190 a). figure 2-15: 5k ? r wb ppm/c vs. wiper setting. (r bw(code=n, 125c) -r bw(code=n, - 40c) )/r bw(code = 256, 25c) /165c * 1,000,000) (v dd = 5.5v, i w = 190 a). figure 2-16: 5k ? r wb ppm/c vs. wiper setting. (r bw(code=n, 125c) -r bw(code=n, - 40c) )/r bw(code = 256, 25c) /165c * 1,000,000) (v dd = 3.0v, i w = 190 a). -2.50% -1.50% -0.50% 0.50% 1.50% 2.50% 0 32 64 96 128 160 192 224 256 wiper code error % -40c +25c +85c +125c -2.50% -1.50% -0.50% 0.50% 1.50% 2.50% 0 32 64 96 128 160 192 224 256 wiper code error % -40c +25c +85c +125c 40 42 44 46 48 50 52 54 0 32 64 96 128 160 192 224 256 wiper code ppm / c ch0 ch1 ch2 ch3 60 65 70 75 80 85 90 95 100 0 32 64 96 128 160 192 224 256 wiper code ppm / c ch0 ch1 ch2 ch3
? 2010 microchip technology inc. ds22265a-page 23 mcp444x/446x note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-17: 5k ? low-voltage decrement wiper settling time (v dd = 2.7v) (1 s/div). figure 2-18: 5k ? low-voltage decrement wiper settling time (v dd = 5.5v) (1 s/div). figure 2-19: 5k ? power-up wiper response time (20 ms/div). figure 2-20: 5k ? low-voltage increment wiper settling time (v dd = 2.7v) (1 s/div). figure 2-21: 5k ? low-voltage increment wiper settling time (v dd = 5.5v) (1 s/div).
mcp444x/446x ds22265a-page 24 ? 2010 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-22: 10 k pot mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 5.5v). figure 2-23: 10 k pot mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 3.0v). figure 2-24: 10 k rheo mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 5.5v). figure 2-25: 10 k rheo mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 3.0v). 20 40 60 80 100 120 0 25 50 75 100 125 150 175 200 225 250 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 60 100 140 180 220 260 300 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 40 60 80 100 120 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -1 -0.5 0 0.5 1 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 60 100 140 180 220 260 300 0 25 50 75 100 125 150 175 200 225 250 wiper setting (decimal) wiper resistance (r w ) (ohms) -2 -1 0 1 2 3 4 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c
? 2010 microchip technology inc. ds22265a-page 25 mcp444x/446x note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-26: 10 k ? nominal resistance (r ab ) ( ) vs. ambient temperature and v dd . figure 2-27: 10 k ? r wb ( ) vs. wiper setting and ambient temperature (v dd = 5.5v, i w = 150 a). figure 2-28: 10 k ? r wb ( ) vs. wiper setting and ambient temperature (v dd = 3.0v, i w = 150 a). 10000 10050 10100 10150 10200 10250 -40 0 40 80 120 ambient temperature (c) nominal resistance (r ab ) (ohms) 5.5v 2.7v 0 2000 4000 6000 8000 10000 12000 0 32 64 96 128 160 192 224 256 wiper code resistance () -40c +25c +85c +125c 0 2000 4000 6000 8000 10000 12000 0 32 64 96 128 160 192 224 256 wiper code resistance () -40c +25c +85c +125c
mcp444x/446x ds22265a-page 26 ? 2010 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-29: 10 k ? worst case r bw from average r bw (r bw0 -r bw3 ) error (%) vs. wiper setting and temperature (v dd = 5.5v, i w = 150 a). figure 2-30: 10 k ? worst case r bw from average r bw (r bw0 -r bw3 ) error (%) vs. wiper setting and temperature (v dd = 3.0v, i w = 150 a). figure 2-31: 10 k ? r wb ppm/c vs. wiper setting. (r bw(code=n, 125c) -r bw(code=n, - 40c) )/r bw(code = 256, 25c) /165c * 1,000,000) (v dd = 5.5v, i w = 150 a). figure 2-32: 10 k ? r wb ppm/c vs. wiper setting. (r bw(code=n, 125c) -r bw(code=n, - 40c) )/r bw(code = 256, 25c) /165c * 1,000,000) (v dd = 3.0v, i w = 150 a). -1.50% -1.00% -0.50% 0.00% 0.50% 1.00% 1.50% 0 32 64 96 128 160 192 224 256 wiper code error % -40c +25c +85c +125c -1.50% -1.00% -0.50% 0.00% 0.50% 1.00% 1.50% 0 32 64 96 128 160 192 224 256 wiper code error % -40c +25c +85c +125c 10 15 20 25 30 35 40 45 50 0 32 64 96 128 160 192 224 256 wiper code ppm / c ch0 ch1 ch2 ch3 20 25 30 35 40 45 50 55 60 0 32 64 96 128 160 192 224 256 wiper code ppm / c ch0 ch1 ch2 ch3
? 2010 microchip technology inc. ds22265a-page 27 mcp444x/446x note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-33: 10 k ? low-voltage decrement wiper settling time (v dd = 2.7v) (1 s/div). figure 2-34: 10 k ? low-voltage decrement wiper settling time (v dd = 5.5v) (1 s/div). figure 2-35: 10 k ? low-voltage increment wiper settling time (v dd = 2.7v) (1 s/div). figure 2-36: 10 k ? low-voltage increment wiper settling time (v dd = 5.5v) (1 s/div).
mcp444x/446x ds22265a-page 28 ? 2010 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-37: 50 k pot mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 5.5v). figure 2-38: 50 k pot mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 3.0v). figure 2-39: 50 k rheo mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 5.5v). figure 2-40: 50 k rheo mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 3.0v). 20 40 60 80 100 120 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 60 100 140 180 220 260 300 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 40 60 80 100 120 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 60 100 140 180 220 260 300 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -1 -0.75 -0.5 -0.25 0 0.25 0.5 0.75 1 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c
? 2010 microchip technology inc. ds22265a-page 29 mcp444x/446x note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-41: 50 k ? nominal resistance (r ab ) ( ) vs. ambient temperature and v dd . figure 2-42: 50 k ? r wb ( ) vs. wiper setting and ambient temperature (v dd = 5.5v, i w = 90 a). figure 2-43: 50 k ? r wb ( ) vs. wiper setting and ambient temperature (v dd = 3.0v, i w = 48 a). 49400 49600 49800 50000 50200 50400 50600 50800 -40 0 40 80 120 ambient temperature (c) nominal resistance (r ab ) (ohms) 2.7v 5.5v 0 10000 20000 30000 40000 50000 60000 0 32 64 96 128 160 192 224 256 wiper code resistance () -40c +25c +85c +125c 0 10000 20000 30000 40000 50000 60000 0 32 64 96 128 160 192 224 256 wiper code resistance () -40c +25c +85c +125c
mcp444x/446x ds22265a-page 30 ? 2010 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-44: 50 k ? worst case r bw from average r bw (r bw0 -r bw3 ) error (%) vs. wiper setting and temperature (v dd = 5.5v, i w = 90 a). figure 2-45: 50 k ? worst case r bw from average r bw (r bw0 -r bw3 ) error (%) vs. wiper setting and temperature (v dd = 3.0v, i w = 48 a). figure 2-46: 50 k ? r wb ppm/c vs. wiper setting. (r bw(code=n, 125c) -r bw(code=n, - 40c) )/r bw(code = 256, 25c) /165c * 1,000,000) (v dd = 5.5v, i w = 90 a). figure 2-47: 50 k ? r wb ppm/c vs. wiper setting. (r bw(code=n, 125c) -r bw(code=n, - 40c) )/r bw(code = 256, 25c) /165c * 1,000,000) (v dd = 3.0v, i w = 48 a). -1.00% 0.00% 1.00% 2.00% 3.00% 4.00% 5.00% 6.00% 7.00% 0 32 64 96 128 160 192 224 256 wiper code error % -40c +25c +85c +125c -2.00% -1.00% 0.00% 1.00% 2.00% 3.00% 4.00% 0 32 64 96 128 160 192 224 256 wiper code error % -40c +25c +85c +125c -3 -2 -1 0 1 2 3 4 5 6 7 0 32 64 96 128 160 192 224 256 wiper code ppm / c ch0 ch1 ch2 ch3 -2 0 2 4 6 8 10 12 0 32 64 96 128 160 192 224 256 wiper code ppm / c ch0 ch1 ch2 ch3
? 2010 microchip technology inc. ds22265a-page 31 mcp444x/446x note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-48: 50 k ? low-voltage decrement wiper settling time (v dd = 2.7v) (1 s/div). figure 2-49: 50 k ? low-voltage decrement wiper settling time (v dd = 5.5v) (1 s/div). figure 2-50: 50 k ? low-voltage increment wiper settling time (v dd = 2.7v) (1 s/div). figure 2-51: 50 k ? low-voltage increment wiper settling time (v dd = 5.5v) (1 s/div).
mcp444x/446x ds22265a-page 32 ? 2010 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-52: 100 k pot mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 5.5v). figure 2-53: 100 k pot mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 3.0v). figure 2-54: 100 k rheo mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 5.5v). figure 2-55: 100 k rheo mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 3.0v). 20 40 60 80 100 120 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.2 -0.1 0 0.1 0.2 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 60 100 140 180 220 260 300 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 40 60 80 100 120 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 60 100 140 180 220 260 300 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (rw) (ohms) -0.6 -0.4 -0.2 0 0.2 0.4 0.6 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c i nl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c
? 2010 microchip technology inc. ds22265a-page 33 mcp444x/446x note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-56: 100 k ? nominal resistance (r ab ) ( ) vs. ambient temperature and v dd . figure 2-57: 100 k ? r wb ( ) vs. wiper setting and ambient temperature (v dd = 5.5v, i w = 45 a). figure 2-58: 100 k ? r wb ( ) vs. wiper setting and ambient temperature (v dd = 3.0v, i w = 24 a). 99000 99500 100000 100500 101000 101500 -40 0 40 80 120 ambient temperature (c) nominal resistance (r ab ) (ohms) 5.5v 2.7v 0 20000 40000 60000 80000 100000 120000 0 32 64 96 128 160 192 224 256 wiper code resistance () -40c +25c +85c +125c 0 20000 40000 60000 80000 100000 120000 0 32 64 96 128 160 192 224 256 wiper code resistance () -40c +25c +85c +125c
mcp444x/446x ds22265a-page 34 ? 2010 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-59: 100 k ? worst case r bw from average r bw (r bw0 -r bw3 ) error (%) vs. wiper setting and temperature (v dd = 5.5v, i w = 45 a). figure 2-60: 100 k ? worst case r bw from average r bw (r bw0 -r bw3 ) error (%) vs. wiper setting and temperature (v dd = 3.0v, i w = 24 a). figure 2-61: 100 k ? r wb ppm/c vs. wiper setting. (r bw(code=n, 125c) -r bw(code=n, - 40c) )/r bw(code = 256, 25c) /165c * 1,000,000) (v dd = 5.5v, i w = 45 a). figure 2-62: 100 k ? r wb ppm/c vs. wiper setting. (r bw(code=n, 125c) -r bw(code=n, - 40c) )/r bw(code = 256, 25c) /165c * 1,000,000) (v dd = 3.0v, i w = 24 a). -1.00% 0.00% 1.00% 2.00% 3.00% 4.00% 5.00% 6.00% 7.00% 8.00% 9.00% 10.00% 11.00% 12.00% 13.00% 14.00% 0 32 64 96 128 160 192 224 256 wiper code error % -40c +25c +85c +125c -1.00% 0.00% 1.00% 2.00% 3.00% 4.00% 5.00% 6.00% 7.00% 0 32 64 96 128 160 192 224 256 wiper code error % -40c +25c +85c +125c 0 2 4 6 8 10 12 14 16 0 32 64 96 128 160 192 224 256 wiper code ppm / c ch0 ch1 ch2 ch3 0 2 4 6 8 10 12 14 16 18 0 32 64 96 128 160 192 224 256 wiper code ppm / c ch0 ch1 ch2 ch3
? 2010 microchip technology inc. ds22265a-page 35 mcp444x/446x note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-63: 100 k ? low-voltage decrement wiper settling time (v dd = 2.7v) (1 s/div). figure 2-64: 100 k ? low-voltage decrement wiper settling time (v dd = 5.5v) (1 s/div). figure 2-65: 100 k ? low-voltage increment wiper settling time (v dd = 2.7v) (1 s/div). figure 2-66: 100 k ? low-voltage increment wiper settling time (v dd = 5.5v) (1 s/div).
mcp444x/446x ds22265a-page 36 ? 2010 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-67: v ih (sda, scl) vs. v dd and temperature. figure 2-68: v il (sda, scl) vs. v dd and temperature. figure 2-69: v ol (sda) vs. v dd and temperature (i ol = 3 ma). 1 1.5 2 2.5 3 3.5 4 -40 0 40 80 120 temperature (c) v ih (v) 5.5v 2.7v 1 1.5 2 -40 0 40 80 120 temperature (c) v il (v) 5.5v 2.7v 50 70 90 110 130 150 170 190 210 230 -40 0 40 80 120 temperature (c) v ol (mv) 5.5v 2.7v
? 2010 microchip technology inc. ds22265a-page 37 mcp444x/446x note: unless otherwise indicated, t a = +25c, v dd =5v, v ss = 0v. figure 2-70: nominal eeprom write cycle time vs. v dd and temperature. figure 2-71: por/bor trip point vs. v dd and temperature. 2.1 test circuits figure 2-72: -3 db gain vs. frequency test. figure 2-73: r bw and r w measurement. 1.5 2.0 2.5 3.0 3.5 4.0 4.5 -40 0 40 80 120 temperature (c) t wc (ms) 2.7v 5.5v 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 -40 0 40 80 120 temperature (c) v dd (v) + - v out 2.5v dc +5v a b w offset gnd v in a b w i w v w floating r bw = v w /i w v a v b r w = (v w -v a )/i w
mcp444x/446x ds22265a-page 38 ? 2010 microchip technology inc. notes:
? 2010 microchip technology inc. ds22265a-page 39 mcp444x/446x 3.0 pin descriptions the descriptions of the pins are listed in table 3-1 . additional descriptions of the device pins follows. table 3-1: pinout description for the mcp444x/446x pin weak pull-up/ down ( note 1 ) standard function tssop qfn symbol i/o buffer type 14l 20l 20l ?119 p3a a analog no potentiometer 3 terminal a 1220 p3w a analog no potentiometer 3 wiper terminal 231 p3b a analog no potentiometer 3 terminal b 342 hvc/a0 i hv w/st ?smart? high voltage command / i 2 c address 0 453 scl i hv w/st no i 2 c clock input 564 sda i hv w/st no i 2 c serial data i/o. open drain output 675 v ss ?p ? ground 786 p1b a analog no potentiometer 1 terminal b 897 p1w a analog no potentiometer 1 wiper terminal ?10 8 p1a a analog no potentiometer 1 terminal a ?11 9 p0a a analog no potentiometer 0 terminal a 91210 p0w a analog no potentiometer 0 wiper terminal 10 13 11 p0b a analog no potentiometer 0 terminal b ?1412 wp i hv w/st ?smart? hardware eeprom write protect ?1513 reset i hv w/st yes hardware reset pin 11 16 14 a1 i hv w/st ?smart? i 2 c address 1 12 17 15 v dd ?p ? positive power supply input 13 18 16 p2b a analog no potentiometer 2 terminal b 14 19 17 p2w a analog no potentiometer 2 wiper terminal ?2018 p2a a analog no potentiometer 2 terminal a ??21 ep ? ? ? exposed pad. ( note 2 ) legend: hv w/st = high voltage tolerant input (with schmidtt trigger input) a = analog pins (potentiometer terminals) i = digital input (high z) o = digital output i/o = input / output p = power note 1: the pin?s ?smart? pull-up shuts off while the pin is forced low. this is done to reduce the standby and shut-down current. 2: the qfn package has a contact on the bottom of the package. this contact is conductively connected to the die substrate, and therefore should be unconnected or connected to the same ground as the device?s v ss pin.
mcp444x/446x ds22265a-page 40 ? 2010 microchip technology inc. 3.1 high voltage command / address 0 (hvc/a0) the hvc/a0 pin is the address 0 input for the i 2 c interface as well as the high voltage command pin. at the device?s por/bor the value of the a0 address bit is latched. this input along with the a1 pin completes the device address. this allows up to 4 mcp44xx devices to be on a single i 2 c bus. during normal operation, the voltage on this pin determines whether the i 2 c command is a normal command or a high voltage command (when hvc/a0 = v ihh ). 3.2 serial clock (scl) the scl pin is the serial interfaces serial clock pin. this pin is connected to the host controllers scl pin. the mcp44xx is a slave device, so its scl pin accepts only external clock signals. 3.3 serial data (sda) the sda pin is the serial interfaces serial data pin. this pin is connected to the host controllers sda pin. the sda pin is an open-drain n-channel driver. 3.4 ground (v ss ) the v ss pin is the device ground reference. 3.5 potentiometer terminal b the terminal b pin is connected to the internal potentiometer?s terminal b. the potentiometer?s terminal b is the fixed connection to the zero scale wiper value of the digital potentiometer. this corresponds to a wiper value of 0x00 for both 7-bit and 8-bit devices. the terminal b pin does not have a polarity relative to the terminal w or a pins. the terminal b pin can support both positive and negative current. the voltage on terminal b must be between v ss and v dd . mcp44xx devices have four terminal b pins, one for each resistor network. 3.6 potentiometer wiper (w) terminal the terminal w pin is connected to the internal potentiometer?s terminal w (the wiper). the wiper terminal is the adjustable terminal of the digital potentiometer. the terminal w pin does not have a polarity relative to terminals a or b pins. the terminal w pin can support both positive and negative current. the voltage on terminal w must be between v ss and v dd . mcp44xx devices have four terminal w pins, one for each resistor network. 3.7 potentiometer terminal a the terminal a pin is available on the mcp44x1 devices, and is connected to the internal potentiometer?s terminal a. the potentiometer?s terminal a is the fixed connection to the full scale wiper value of the digital potentiometer. this corresponds to a wiper value of 0x100 for 8-bit devices or 0x80 for 7-bit devices. the terminal a pin does not have a polarity relative to the terminal w or b pins. the terminal a pin can support both positive and negative current. the voltage on terminal a must be between v ss and v dd . the terminal a pin is not available on the mcp44x2 devices, and the internally terminal a signal is floating. mcp44x1 devices have four terminal a pins, one for each resistor network. terminal a is not available on the mcp44x2 devices. 3.8 write protect (wp ) the wp pin is used to force the nonvolatile memory to be write protected. 3.9 reset (reset ) the reset pin is used to force the device into the por/bor state. 3.10 address 1 (a1) the a1 pin is the i 2 c interface?s address 1 pin. along with the a0 pins, up to 4 mcp44xx devices can be on a single i 2 c bus. 3.11 positive power supply input (v dd ) the v dd pin is the device?s positive power supply input. the input power supply is relative to v ss . while the device v dd < v min (2.7v), the electrical performance of the device may not meet the data sheet specifications. 3.12 no connect (nc) these pins should be either connected to v dd or v ss . 3.13 exposed pad (ep) this pad is conductively connected to the device's substrate. this pad should be tied to the same potential as the v ss pin (or left unconnected). this pad could be used to assist as a heat sink for the device when connected to a pcb heat sink.
? 2010 microchip technology inc. ds22265a-page 41 mcp444x/446x 4.0 functional overview this data sheet covers a family of four nonvolatile dig- ital potentiometer and rheostat devices that will be referred to as mcp44xx. the mcp44x1 devices are the potentiometer configuration, while the mcp44x2 devices are the rheostat configuration. as the device block diagram shows, there are four main functional blocks. these are: ? por/bor and reset operation ? memory map ? resistor network ? serial interface (i 2 c) the por/bor operation and the memory map are discussed in this section and the resistor network and i 2 c operation are described in their own sections. the device commands commands are discussed in section 7.0 . 4.1 por/bor and reset operation the power-on reset is the case where the device is having power applied to it from v ss . the brown-out reset occurs when a device had power applied to it, and that power (voltage) drops below the specified range. the devices ram retention voltage (v ram ) is lower than the por/bor voltage trip point (v por /v bor ). the maximum v por /v bor voltage is less then 1.8v. when v por /v bor < v dd < 2.7v, the electrical performance may not meet the data sheet specifications. in this region, the device is capable of reading and writing to its eeprom and incrementing, decrementing, reading and writing to its volatile memory if the proper serial command is executed. when v dd < v por /v bor or the reset pin is low, the pin weak pull-ups are enabled. 4.1.1 power-on reset when the device powers up, the device v dd will cross the v por /v bor voltage. once the v dd voltage crosses the v por /v bor voltage, the following happens: ? the volatile wiper register is loaded with value in the corresponding nonvolatile wiper register ? the tcon registers are loaded with their default value ? the device is capable of digital operation 4.1.2 brown-out reset when the device powers down, the device v dd will cross the v por /v bor voltage. once the v dd voltage decreases below the v por /v bor voltage, the following happens: ? serial interface is disabled ? eeprom writes are disabled if the v dd voltage decreases below the v ram voltage, the following happens: ? volatile wiper registers may become corrupted ? tcon registers may become corrupted as the voltage recovers above the v por /v bor voltage, see section 4.1.1 ?power-on reset? . serial commands not completed due to a brown-out condition may cause the memory location (volatile and nonvolatile) to become corrupted. 4.1.3 reset pin the reset pin can be used to force the device into the por/bor state of the device. when the reset pin is forced low, the device is forced into the reset state. this means that the tcon and status registers are forced to their default values and the volatile wiper registers are loaded with the value in the corresponding nonvolatile wiper register. also the i 2 c interface is disabled. any nonvolatile write cycle is not interrupted, and allowed to complete. this feature allows a hardware method for all registers to be updated at the same time. 4.1.4 interaction of reset pin and bor/por circuitry figure 4-1 shows how the reset pin signal and the por/bor signal interact to control the hardware reset state of the device. figure 4-1: por/bor signal and reset pin interaction. reset (from pin) por/bor signal device reset
mcp444x/446x ds22265a-page 42 ? 2010 microchip technology inc. 4.2 memory map the device memory has 16 locations that are 9-bit wide (16x9 bits). this memory space contains both volatile and nonvolatile locations (see tab l e 4 - 1 ). table 4-1: memory map and the supported commands address function memory type allowed commands disallowed commands (2) factory initialization 00h volatile wiper 0 ram read, write, increment, decrement ? ? 01h volatile wiper 1 ram read, write, increment, decrement ? ? 02h nonvolatile wiper 0 eeprom read, write (1) increment, decrement 8-bit 80h 7-bit 40h 03h nonvolatile wiper 1 eeprom read, write (1) increment, decrement 8-bit 80h 7-bit 40h 04h volatile tcon0 register ram read, write increment, decrement ? 05h status register ram read write, increment, decrement ? 06h volatile wiper 2 ram read, write, increment, decrement ? ? 07h volatile wiper 3 ram read, write, increment, decrement ? ? 08h nonvolatile wiper 2 eeprom read, write (1) increment, decrement 8-bit 80h 7-bit 40h 09h nonvolatile wiper 3 eeprom read, write (1) increment, decrement 8-bit 80h 7-bit 40h 0ah volatile tcon1 register ram read, write increment, decrement ? 0bh data eeprom eeprom read, write (1) increment, decrement 000h 0ch data eeprom eeprom read, write (1) increment, decrement 000h 0dh data eeprom eeprom read, write (1) increment, decrement 000h 0eh data eeprom eeprom read, write (1) increment, decrement 000h 0fh data eeprom eeprom read, write (1) increment, decrement 000h note 1: when an eeprom write is active, these are invalid commands and will generate an error condition. the user should use a read of the status register to determine when the write cycle has completed. to exit the error condition, the user must take the hvc pin to the v ih level and then back to the active state (v il or v ihh ). 2: this command on this address will generate an error condition. to exit the error condition, the user must take the hvc pin to the v ih level and then back to the active state (v il or v ihh ).
? 2010 microchip technology inc. ds22265a-page 43 mcp444x/446x 4.2.1 nonvolatile memory (eeprom) this memory can be grouped into two uses of nonvolatile memory. these are: ? general purpose registers ? nonvolatile wiper registers the nonvolatile wipers start functioning below the devices v por /v bor trip point. 4.2.1.1 general purpose registers these locations allow the user to store up to 5 (9-bit) locations worth of information. 4.2.1.2 nonvolatile wiper registers these locations contain the wiper values that are loaded into the corresponding volatile wiper register whenever the device has a por/bor event. there are four registers, one for each resistor network. the nonvolatile wiper register enables stand-alone operation of the device (without microcontroller control) after being programmed to the desired value. 4.2.1.3 factory initialization of nonvolatile memory (eeprom) the nonvolatile wiper values will be initialized to mid-scale value. this is shown in tab l e 4 - 2 . the general purpose eeprom memory will be programmed to a default value of 0x000. it is good practice in the manufacturing flow to configure the device to your desired settings. table 4-2: default factory settings selection 4.2.1.4 special features there are 5 nonvolatile bits that are not directly mapped into the address space. these bits control the following functions: ? eeprom write protect ? wiperlock technology for nonvolatile wiper 0 ? wiperlock technology for nonvolatile wiper 1 ? wiperlock technology for nonvolatile wiper 2 ? wiperlock technology for nonvolatile wiper 3 the operation of wiperlock technology is discussed in section 5.3 . the state of the wl0, wl1, wl2, wl3, and wp bits is reflected in the status register (see register 4-1 ). eeprom write protect all internal eeprom memory can be write protected. when eeprom memory is write protected, write commands to the internal eeprom are prevented. write protect (wp ) can be enabled/disabled by two methods. these are: ?external wp hardware pin (mcp44x1 devices only) ? nonvolatile configuration bit (wp) high voltage commands are required to enable and disable the nonvolatile wp bit. these commands are shown in section 7.8 ?modify write protect or wiperlock technology (high voltage)? . to write to eeprom, both the external wp pin and the internal wp eeprom bit must be disabled. write protect does not block commands to the volatile registers. 4.2.2 volatile memory (ram) there are seven volatile memory locations. these are: ? volatile wiper 0 ? volatile wiper 1 ? volatile wiper 2 ? volatile wiper 3 ? status register ? terminal control (tcon0) register 0 ? terminal control (tcon)1 register 1 the volatile memory starts functioning at the ram retention voltage (v ram ). resistance code typical r ab value default por wiper setting wiper code wiperlock tm technology and write protect setting 8-bit 7-bit -502 5.0 k mid scale 80h 40h disabled -103 10.0 k mid scale 80h 40h disabled -503 50.0 k mid scale 80h 40h disabled -104 100.0 k mid scale 80h 40h disabled
mcp444x/446x ds22265a-page 44 ? 2010 microchip technology inc. 4.2.2.1 status (status) register this register contains 7 status bits. these bits show the state of the wiperlock bits, the write protect bit, and if an eeprom write cycle is active. the status register can be accessed via the read commands. register 4- 1 describes each status register bit. the status register is placed at address 05h. register 4-1: status register r-1 r-1 r-1 r-1 r-0 r-x r-x r-1 r-x d8:d7 wl3 (1) wl2 (1) eewa wl1 (1) wl0 (1) ?wp (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 8-7 d8:d7: reserved. forced to ?1? bit 6 wl3: wiperlock status bit for resistor network 3 (refer to section 5.3 ?wiperlock technology? for further information) the wiperlock technology bit (wl3) prevents the volatile and nonvolatile wiper 3 addresses and the tcon1 register bits r3hw, r3a, r3w, and r3b from being written to. high voltage commands are required to enable and disable wiperlock technology. 1 = wiper and tcon1 register bits r3hw, r3a, r3w, and r3b of resistor network 3 (pot 3) are ?locked? (write protected) 0 = wiper and tcon1 of resistor network 3 (pot 3) can be modified note: the wl3 bit always reflects the result of the last programming cycle to the nonvolatile wl3 bit. after a por/bor or reset pin event, the wl3 bit is loaded with the nonvolatile wl3 bit value. bit 5 wl2: wiperlock status bit for resistor network 2 (refer to section 5.3 ?wiperlock technology? for further information) the wiperlock technology bit (wl2) prevents the volatile and nonvolatile wiper 2 addresses and the tcon1 register bits r2hw, r2a, r2w, and r2b from being written to. high voltage commands are required to enable and disable wiperlock technology. 1 = wiper and tcon1 register bits r2hw, r2a, r2w, and r2b of resistor network 2 (pot 2) are ?locked? (write protected) 0 = wiper and tcon1 of resistor network 2 (pot 2) can be modified note: the wl0 bit always reflects the result of the last programming cycle to the nonvolatile wl0 bit. after a por/bor or reset pin event, the wl0 bit is loaded with the nonvolatile wl0 bit value. bit 4 eewa: eeprom write active status bit this bit indicates if the eeprom write cycle is occurring. 1 = an eeprom write cycle is currently occurring. only serial commands to the volatile memory locations are allowed (addresses 00h, 01h, 04h, and 05h) 0 = an eeprom write cycle is not currently occurring note 1: requires a high voltage command to modify the state of this bit (for nonvolatile devices only). this bit is not directly written, but reflects the system state (for this feature).
? 2010 microchip technology inc. ds22265a-page 45 mcp444x/446x bit 3 wl1: wiperlock status bit for resistor network 1 (refer to section 5.3 ?wiperlock technology? for further information) the wiperlock technology bit (wl1) prevents the volatile and nonvolatile wiper 1 addresses and the tcon0 register bits r1hw, r1a, r1w, and r1b from being written to. high voltage commands are required to enable and disable wiperlock technology. 1 = wiper and tcon0 register bits r1hw, r1a, r1w, and r1b of resistor network 1 (pot 1) are ?locked? (write protected) 0 = wiper and tcon0 of resistor network 1 (pot 1) can be modified note: the wl1 bit always reflects the result of the last programming cycle to the nonvolatile wl1 bit. after a por/bor or reset pin event, the wl1 bit is loaded with the nonvolatile wl1 bit value. bit 2 wl0: wiperlock status bit for resistor network 0 (refer to section 5.3 ?wiperlock technology? for further information) the wiperlock technology bit (wl0) prevents the volatile and nonvolatile wiper 0 addresses and the tcon0 register bits r0hw, r0a, r0w, and r0b from being written to. high voltage commands are required to enable and disable wiperlock technology. 1 = wiper and tcon0 register bits r0hw, r0a, r0w, and r0b of resistor network 0 (pot 0) are ?locked? (write protected) 0 = wiper and tcon0 of resistor network 0 (pot 0) can be modified note: the wl0 bit always reflects the result of the last programming cycle to the nonvolatile wl0 bit. after a por/bor or reset pin event, the wl0 bit is loaded with the nonvolatile wl0 bit value. bit 1 reserved: forced to ? 1 ? bit 0 wp: eeprom write protect status bit (refer to section ?eeprom write protect? for further information) this bit indicates the status of the write protection on the eeprom memory. when write protect is enabled, writes to all nonvolatile memory are prevented. this includes the general purpose eeprom memory, and the nonvolatile wiper registers. write protect does not block modification of the volatile wiper register values or the volatile tcon0 and tcon1 register values (via increment, decrement, or write commands). this status bit is an or of the devices write protect pin (wp ) and the internal nonvolatile wp bit. high voltage commands are required to enable and disable the internal wp eeprom bit. 1 = eeprom memory is write protected 0 = eeprom memory can be written register 4-1: status register (continued) note 1: requires a high voltage command to modify the state of this bit (for nonvolatile devices only). this bit is not directly written, but reflects the system state (for this feature).
mcp444x/446x ds22265a-page 46 ? 2010 microchip technology inc. 4.2.2.2 terminal control (tcon) registers there are two terminal control (tcon) registers. these are called tcon0 and tcon1. each register contains 8 control bits, four bits for each wiper. register 4-2 describes each bit of the tcon0 register, while register 4-3 describes each bit of the tcon1 register. the state of each resistor network terminal connection is individually controlled. that is, each terminal connection (a, b and w) can be individually connected/ disconnected from the resistor network. this allows the system to minimize the currents through the digital potentiometer. the value that is written to the specified tcon register will appear on the appropriate resistor network terminals when the serial command has completed. when the wl1 bit is enabled, writes to the tcon0 register bits r1hw, r1a, r1w, and r1b are inhibited. when the wl0 bit is enabled, writes to the tcon0 register bits r0hw, r0a, r0w, and r0b are inhibited. when the wl3 bit is enabled, writes to the tcon1 register bits r3hw, r3a, r3w, and r3b are inhibited. when the wl2 bit is enabled, writes to the tcon1 register bits r2hw, r2a, r2w, and r2b are inhibited. on a por/bor these registers are loaded with 1ffh (9-bit), for all terminals connected. the host controller needs to detect the por/bor event and then update the volatile tcon register values.
? 2010 microchip technology inc. ds22265a-page 47 mcp444x/446x register 4-2: tcon0 bits (1) r-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 d8 r1hw r1a r1w r1b r0hw r0a r0w r0b bit 8 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 8 d8: reserved. forced to ?1? bit 7 r1hw: resistor 1 hardware configuration control bit this bit forces resistor 1 into the ?shutdown? configuration of the hardware pin 1 = resistor 1 is not forced to the hardware pin ?shutdown? configuration 0 = resistor 1 is forced to the hardware pin ?shutdown? configuration bit 6 r1a: resistor 1 terminal a (p1a pin) connect control bit this bit connects/disconnects the resistor 1 terminal a to the resistor 1 network 1 = p1a pin is connected to the resistor 1 network 0 = p1a pin is disconnected from the resistor 1 network bit 5 r1w: resistor 1 wiper (p1w pin) connect control bit this bit connects/disconnects the resistor 1 wiper to the resistor 1 network 1 = p1w pin is connected to the resistor 1 network 0 = p1w pin is disconnected from the resistor 1 network bit 4 r1b: resistor 1 terminal b (p1b pin) connect control bit this bit connects/disconnects the resistor 1 terminal b to the resistor 1 network 1 = p1b pin is connected to the resistor 1 network 0 = p1b pin is disconnected from the resistor 1 network bit 3 r0hw: resistor 0 hardware configuration control bit this bit forces resistor 0 into the ?shutdown? configuration of the hardware pin 1 = resistor 0 is not forced to the hardware pin ?shutdown? configuration 0 = resistor 0 is forced to the hardware pin ?shutdown? configuration bit 2 r0a: resistor 0 terminal a (p0a pin) connect control bit this bit connects/disconnects the resistor 0 terminal a to the resistor 0 network 1 = p0a pin is connected to the resistor 0 network 0 = p0a pin is disconnected from the resistor 0 network bit 1 r0w: resistor 0 wiper (p0w pin) connect control bit this bit connects/disconnects the resistor 0 wiper to the resistor 0 network 1 = p0w pin is connected to the resistor 0 network 0 = p0w pin is disconnected from the resistor 0 network bit 0 r0b: resistor 0 terminal b (p0b pin) connect control bit this bit connects/disconnects the resistor 0 terminal b to the resistor 0 network 1 = p0b pin is connected to the resistor 0 network 0 = p0b pin is disconnected from the resistor 0 network note 1: these bits do not affect the wiper register values.
mcp444x/446x ds22265a-page 48 ? 2010 microchip technology inc. register 4-3: tcon1 bits (1) r-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 d8 r3hw r3a r3w r3b r2hw r2a r2w r2b bit 8 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 8 d8: reserved. forced to ?1? bit 7 r3hw: resistor 3 hardware configuration control bit this bit forces resistor 3 into the ?shutdown? configuration of the hardware pin 1 = resistor 3 is not forced to the hardware pin ?shutdown? configuration 0 = resistor 3 is forced to the hardware pin ?shutdown? configuration bit 6 r3a: resistor 3 terminal a (p3a pin) connect control bit this bit connects/disconnects the resistor 3 terminal a to the resistor 3 network 1 = p3a pin is connected to the resistor 3 network 0 = p3a pin is disconnected from the resistor 3 network bit 5 r3w: resistor 3 wiper (p3w pin) connect control bit this bit connects/disconnects the resistor 3 wiper to the resistor 3 network 1 = p3w pin is connected to the resistor 3 network 0 = p3w pin is disconnected from the resistor 3 network bit 4 r3b: resistor 3 terminal b (p3b pin) connect control bit this bit connects/disconnects the resistor 3 terminal b to the resistor 3 network 1 = p3b pin is connected to the resistor 3 network 0 = p3b pin is disconnected from the resistor 3 network bit 3 r2hw: resistor 2 hardware configuration control bit this bit forces resistor 2 into the ?shutdown? configuration of the hardware pin 1 = resistor 2 is not forced to the hardware pin ?shutdown? configuration 0 = resistor 2 is forced to the hardware pin ?shutdown? configuration bit 2 r2a: resistor 2 terminal a (p0a pin) connect control bit this bit connects/disconnects the resistor 2 terminal a to the resistor 2 network 1 = p2a pin is connected to the resistor 2 network 0 = p2a pin is disconnected from the resistor 2 network bit 1 r2w: resistor 2 wiper (p0w pin) connect control bit this bit connects/disconnects the resistor 2 wiper to the resistor 2 network 1 = p2w pin is connected to the resistor 2 network 0 = p2w pin is disconnected from the resistor 2 network bit 0 r2b: resistor 2 terminal b (p2b pin) connect control bit this bit connects/disconnects the resistor 2 terminal b to the resistor 2 network 1 = p2b pin is connected to the resistor 2 network 0 = p2b pin is disconnected from the resistor 2 network note 1: these bits do not affect the wiper register values.
? 2010 microchip technology inc. ds22265a-page 49 mcp444x/446x 5.0 resistor network the resistor network has either 7-bit or 8-bit resolution. each resistor network allows zero scale to full scale connections. figure 5-1 shows a block diagram for the resistive network of a device. the resistor network is made up of several parts. these include: ? resistor ladder ?wiper ? shutdown (terminal connections) devices have four resistor networks. these are referred to as pot 0, pot 1 pot 2, and pot 3. figure 5-1: resistor block diagram. 5.1 resistor ladder module the resistor ladder is a series of equal value resistors (r s ) with a connection point (tap) between the two resistors. the total number of resistors in the series (ladder) determines the r ab resistance (see figure 5- 1 ). the end points of the resistor ladder are connected to analog switches which are connected to the device terminal a and terminal b pins. the r ab (and r s ) resistance has small variations over voltage and temperature. for an 8-bit device, there are 256 resistors in a string between terminal a and terminal b. the wiper can be set to tap onto any of these 256 resistors, thus providing 257 possible settings (including terminal a and terminal b). for a 7-bit device, there are 128 resistors in a string between terminal a and terminal b. the wiper can be set to tap onto any of these 128 resistors, thus providing 129 possible settings (including terminal a and terminal b). equation 5-1 shows the calculation for the step resistance. equation 5-1: r s calculation r s a r s r s r s b 257 256 255 1 0 r w (1) w (01h) analog mux r w (1) (00h) r w (1) (feh) r w (1) (ffh) r w (1) (100h) note 1: the wiper resistance is dependent on several factors including, wiper code, device v dd , terminal voltages (on a, b, and w), and temperature. also for the same conditions, each tap selection resistance has a small variation. this r w variation has greater effects on some specifications (such as inl) for the smaller resistance devices (5.0 k ) compared to larger resistance devices (100.0 k ). r ab 8-bit n = 128 127 126 1 0 (01h) (00h) (7eh) (7fh) (80h) 7-bit n = r s r ab 256 () ------------- = r s r ab 128 () ------------- - = 8-bit device 7-bit device
mcp444x/446x ds22265a-page 50 ? 2010 microchip technology inc. 5.2 wiper each tap point (between the r s resistors) is a connection point for an analog switch. the opposite side of the analog switch is connected to a common signal which is connected to the terminal w (wiper) pin. a value in the volatile wiper register selects which analog switch to close, connecting the w terminal to the selected node of the resistor ladder. the wiper can connect directly to terminal b or to terminal a. a zero scale connections, connects the terminal w (wiper) to terminal b (wiper setting of 000h). a full scale connection, connects the terminal w (wiper) to terminal a (wiper setting of 100h or 80h). in these configurations, the only resistance between the terminal w and the other terminal (a or b) is that of the analog switches. a wiper setting value greater than full scale (wiper setting of 100h for 8-bit device or 80h for 7-bit devices) will also be a full scale setting (terminal w (wiper) connected to terminal a). ta b l e 5 - 1 illustrates the full wiper setting map. equation 5-2 illustrates the calculation used to determine the resistance between the wiper and terminal b. equation 5-2: r wb calculation table 5-1: volatile wiper value vs. wiper position map 5.3 wiperlock technology the mcp44xx device?s wiperlock technology allows application-specific calibration settings to be secured in the eeprom without requiring the use of an additional write-protect pin. there are four wiperlock technology configuration bits (wl0, wl1, wl2, and wl3). these bits prevent the nonvolatile and volatile addresses and bits for the specified resistor network from being writ- ten. the wiperlock technology prevents the serial commands from doing the following: ? changing a volatile wiper value ? writing to the specified nonvolatile wiper memory location ? changing the related volatile tcon register bits for either resistor network 0, resistor network 1, resistor network 2, or resistor network 3 (potx), the wlx bit controls the following: ? nonvolatile wiper register ? volatile wiper register ? volatile tcon register bits rxhw, rxa, rxw, and rxb high voltage commands are required to enable and disable wiperlock. please refer to the modify write protect or wiperlock technology (high voltage) command for operation. 5.3.1 por/bor operation when wiperlock technology enabled the wiperlock technology state is not affected by a por/bor event. a por/bor event will load the volatile wiper register value with the nonvolatile wiper register value, refer to section 4.1 . wiper setting properties 7-bit 8-bit 3ffh ? 081h 3ffh ? 101h reserved (full scale (w = a)), increment and decrement commands ignored 080h 100h full scale (w = a), increment commands ignored 07fh ? 041h 0ffh ? 081h w = n 040h 080h w = n (mid scale) 03fh ? 001h 07fh ? 001h w = n 000h 000h zero scale (w = b) decrement command ignored r wb r ab n 256 () ------------- -r w + = n = 0 to 256 (decimal) r wb r ab n 128 () ------------- -r w + = n = 0 to 128 (decimal) 8-bit device 7-bit device
? 2010 microchip technology inc. ds22265a-page 51 mcp444x/446x 5.4 shutdown shutdown is used to minimize the device?s current consumption. the mcp44xx has one method to achieve this. this is: ? terminal control register (tcon) this is different from the mcp42xxx devices in that the hardware shutdown pin (shdn ) has been replaced by a reset pin. the hardware shutdown pin function is still available via software commands to the tcon register. 5.4.1 terminal control register (tcon) the terminal control (tcon) register is a volatile register used to configure the connection of each resistor network terminal pin (a, b, and w) to the resistor network. these registers are shown in register 4-2 and register 4-3 . the rxhw bits forces the selected resistor network into the same state as the mcp42x1?s shdn pin. alternate low power configurations may be achieved with the rxa, rxw, and rxb bits. when the rxhw bit is ? 0 ?: ? the p0a, p1a, p2a, and p3a terminals are disconnected ? the p0w, p1w, p2w, and p3w terminals are simultaneously connect to the p0b, p1b, p2b, and p3b terminals, respectively (see figure 5-2 ) the rxhw bit does not corrupt the values in the volatile wiper registers nor the tcon register. when the shutdown mode is exited (rxhw bit = ? 1 ?): ? the device returns to the wiper setting specified by the volatile wiper value ? the tcon register bits return to controlling the terminal connection state figure 5-2: resistor network shutdown state (rxhw = ? 0 ?). note: when the rxhw bit forces the resistor network into the hardware shdn state, the state of the tcon0 or tcon1 register?s rxa, rxw, and rxb bits is overridden (ignored). when the state of the rxhw bit no longer forces the resistor network into the hardware shdn state, the tcon0 or tcon1 register?s rxa, rxw, and rxb bits return to controlling the terminal connection state. in other words, the rxhw bit does not corrupt the state of the rxa, rxw, and rxb bits. a b w resistor network
mcp444x/446x ds22265a-page 52 ? 2010 microchip technology inc. notes:
? 2010 microchip technology inc. ds22265a-page 53 mcp444x/446x 6.0 serial interface (i 2 c) the mcp44xx devices support the i 2 c serial protocol. the mcp44xx i 2 c?s module operates in slave mode (does not generate the serial clock). figure 6-1 shows a typical i 2 c interface connection. all i 2 c interface signals are high-voltage tolerant. the mcp44xx devices use the two-wire i 2 c serial interface. this interface can operate in standard, fast or high-speed mode. a device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. the bus has to be controlled by a master device which generates the serial clock (scl), controls the bus access and generates the start and stop conditions. the mcp44xx device works as slave. both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. communication is initiated by the master (microcontroller) which sends the start bit, followed by the slave address byte. the first byte transmitted is always the slave address byte, which contains the device code, the address bits, and the r/w bit. refer to the phillips i 2 c document for more details of the i 2 c specifications. figure 6-1: typical i 2 c interface block diagram. 6.1 signal descriptions the i 2 c interface uses up to four pins (signals). these are: ? sda (serial data) ? scl (serial clock) ? a0 (address 0 bit) ? a1 (address 1 bit) 6.1.1 serial data (sda) the serial data (sda) signal is the data signal of the device. the value on this pin is latched on the rising edge of the scl signal when the signal is an input. with the exception of the start and stop conditions, the high or low state of the sda pin can only change when the clock signal on the scl pin is low. during the high period of the clock, the sda pin?s value (high or low) must be stable. changes in the sda pin?s value while the scl pin is high will be interpreted as a start or a stop condition. 6.1.2 serial clock (scl) the serial clock (scl) signal is the clock signal of the device. the rising edge of the scl signal latches the value on the sda pin. the mcp44xx supports three i 2 c interface clock modes: ? standard mode: clock rates up to 100 khz ? fast mode: clock rates up to 400 khz ? high-speed mode (hs mode): clock rates up to 3.4 mhz the mcp44xx will not stretch the clock signal (scl) since memory read access occur fast enough. depending on the clock rate mode, the interface will display different characteristics. 6.1.3 the address bits (a1:a0) there are up to two hardware pins used to specify the device address. the number of address pins is determined by the part number. address 0 is multiplexed with the high voltage command (hvc) function. so the state of a0 is latched on the mcp4xxx?s por/bor event. the state of the a1 pin should be static, that is they should be tied high or tied low. 6.1.3.1 the high voltage command (hvc) signal the high voltage command (hvc) signal is multiplexed with address 0 (a0) and is used to indicate that the command, or sequence of commands, are in the high voltage mode. high voltage commands allow the device?s wiperlock technology and write protect features to be enabled and disabled. the hvc pin has an internal resistor connection to the mcp44xxs internal v dd signal. scl scl mcp4xxx sda sda hvc/a0 (2) i/o (1) host controller typical i 2 c interface connections note 1: if high voltage commands are desired, some type of external circuitry needs to be implemented. 2: these pins have internal pull-ups. if faster rise times are required, then external pull-ups should be added. 3: this pin could be tied high, low, or connected to an i/o pin of the host controller. a1 (2, 3)
mcp444x/446x ds22265a-page 54 ? 2010 microchip technology inc. 6.2 i 2 c operation the mcp44xx?s i 2 c module is compatible with the philips i 2 c specification. the following lists some of the modules features: ? 7-bit slave addressing ? supports three clock rate modes: - standard mode, clock rates up to 100 khz - fast mode, clock rates up to 400 khz - high-speed mode (hs mode), clock rates up to 3.4 mhz ? support multi-master applications ? general call addressing ? internal weak pull-ups on interface signals the i 2 c 10-bit addressing mode is not supported. the philips i 2 c specification only defines the field types, field lengths, timings, etc. of a frame. the frame content defines the behavior of the device. the frame content for the mcp44xx is defined in section 7.0 . 6.2.1 i 2 c bit states and sequence figure 6-8 shows the i 2 c transfer sequence. the serial clock is generated by the master. the following defini- tions are used for the bit states: ? start bit (s) ? data bit ? acknowledge (a) bit (driven low) / no acknowledge (a ) bit (not driven low) ? repeated start bit (sr) ? stop bit (p) 6.2.1.1 start bit the start bit (see figure 6-2 ) indicates the beginning of a data transfer sequence. the start bit is defined as the sda signal falling when the scl signal is ?high?. figure 6-2: start bit. 6.2.1.2 data bit the sda signal may change state while the scl signal is low. while the scl signal is high, the sda signal must be stable (see figure 6-5 ). figure 6-3: data bit. 6.2.1.3 acknowledge (a) bit the a bit (see figure 6-4 ) is typically a response from the receiving device to the transmitting device. depending on the context of the transfer sequence, the a bit may indicate different things. typically the slave device will supply an a response after the start bit and 8 ?data? bits have been received. an a bit has the sda signal low. figure 6-4: acknowledge waveform. not a (a ) response the a bit has the sda signal high. table 6-1 shows some of the conditions where the slave device will issue a not a (a ). if an error condition occurs (such as an a instead of a), then an start bit must be issued to reset the command state machine. table 6-1: mcp45xx/mcp46xx a / a responses sda scl s 1st bit 2nd bit sda scl data bit 1st bit 2nd bit event acknowledge bit response comment general call a only if gcen bit is set slave address valid a slave address not valid a device mem- ory address and specified command (ad3:ad0 and c1:c0) are an invalid combi- nation a after device has received address and command communica- tion during eeprom write cycle a after device has received address and command, and valid condi- tions for eeprom write bus collision n.a. i 2 c module resets, or a ?don?t care? if the colli- sion occurs on the master?s ?start bit? a 8 d0 9 sda scl
? 2010 microchip technology inc. ds22265a-page 55 mcp444x/446x 6.2.1.4 repeated start bit the repeated start bit (see figure 6-5 ) indicates the current master device wishes to continue communicat- ing with the current slave device without releasing the i 2 c bus. the repeated start condition is the same as the start condition, except that the repeated start bit follows a start bit (with the data bits + a bit) and not a stop bit. the start bit is the beginning of a data transfer sequence and is defined as the sda signal falling when the scl signal is ?high?. figure 6-5: repeat start condition waveform. 6.2.1.5 stop bit the stop bit (see figure 6-6 ) indicates the end of the i 2 c data transfer sequence. the stop bit is defined as the sda signal rising when the scl signal is ?high?. a stop bit resets the i 2 c interface of all mcp44xx devices. figure 6-6: stop condition receive or transmit mode. 6.2.2 clock stretching ?clock stretching? is something that the receiving device can do, to allow additional time to ?respond? to the ?data? that has been received. the mcp44xx will not stretch the clock signal (scl) since memory read access occur fast enough. 6.2.3 aborting a transmission if any part of the i 2 c transmission does not meet the command format, it is aborted. this can be intentionally accomplished with a start or stop condition. this is done so that noisy transmissions (usually an extra start or stop condition) are aborted before they corrupt the device. figure 6-7: typical 8-bit i 2 c waveform format. figure 6-8: i 2 c data states and bit sequence. note 1: a bus collision during the repeated start condition occurs if: ? sda is sampled low when scl goes from low to high. ? scl goes low before sda is asserted low. this may indicate that another master is attempting to transmit a data "1". sda scl sr = repeated start 1st bit scl sda a / a p 1st bit sda scl s 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit p a / a scl sda start condition stop condition data allowed to change data or a valid
mcp444x/446x ds22265a-page 56 ? 2010 microchip technology inc. 6.2.4 addressing the address byte is the first byte received following the start condition from the master device. the address contains four (or more) fixed bits and (up to) three user defined hardware address bits (pins a1 and a0). these 7-bits address the desired i 2 c device. the a6:a2 address bits are fixed to ? 01011 ? and the device appends the value of following two address pins (a1 and a0). since there are address bits controlled by hardware pins, there may be up to four mcp44xx devices on the same i 2 c bus. figure 6-9 shows the slave address byte format, which contains the seven address bits. there is also a read/ write (r/w ) bit. tab le 6 -2 shows the fixed address for device. hardware address pins the hardware address bits (a1, and a0) correspond to the logic level on the associated address pins. this allows up to eight devices on the bus. these pins have a weak pull-up enabled when the v dd < v bor . the weak pull-up utilizes the ?smart? pull-up technology and exhibits the same characteristics as the high-voltage tolerant i/o structure. the state of the a0 address pin is latch on por/bor. this is required since high voltage commands force this pin (hvc/a0) to the v ihh level. figure 6-9: slave address bits in the i 2 c control byte. table 6-2: device slave addresses 6.2.5 slope control the mcp44xx implements slope control on the sda output. as the device transitions from hs mode to fs mode, the slope control parameter will change from the hs specification to the fs specification. for fast (fs) and high-speed (hs) modes, the device has a spike suppression and a schmidt trigger at sda and scl inputs. device address comment mcp44xx ? 0101 1 ?b + a1:a0 supports up to 4 devices. ( note 1 ) note 1: a0 is used for high-voltage commands (hvc/a0) and the value is latched at por/bor. sa6a5a4a3a2 a1 a0 r/w a/a start bit slave address r/w bit a bit (controlled by slave device) r/w = 0 = write r/w = 1 = read a = 0 = slave device acknowledges byte a = 1 = slave device does not acknowledge byte ?0? ?1? ?0? ?1? see table 6-2 ?1?
? 2010 microchip technology inc. ds22265a-page 57 mcp444x/446x 6.2.6 hs mode the i 2 c specification requires that a high-speed mode device must be ?activated? to operate in high-speed (3.4 mbit/s) mode. this is done by the master sending a special address byte following the start bit. this byte is referred to as the high-speed master mode code (hsmmc). the mcp44xx device does not acknowledge this byte. however, upon receiving this command, the device switches to hs mode. the device can now communicate at up to 3.4 mbit/s on sda and scl lines. the device will switch out of the hs mode on the next stop condition. the master code is sent as follows: 1. start condition (s) 2. high-speed master mode code ( 0000 1xxx ), the xxx bits are unique to the high-speed (hs) mode master. 3. no acknowledge (a ) after switching to the high-speed mode, the next transferred byte is the i 2 c control byte, which specifies the device to communicate with, and any number of data bytes plus acknowledgements. the master device can then either issue a repeated start bit to address a different device (at high-speed) or a stop bit to return to fast/standard bus speed. after the stop bit, any other master device (in a multi-master system) can arbitrate for the i 2 c bus. see figure 6-10 for illustration of hs mode command sequence. for more information on the hs mode, or other i 2 c modes, please refer to the phillips i 2 c specification. 6.2.6.1 slope control the slope control on the sda output is different between the fast/standard speed and the high-speed clock modes of the interface. 6.2.6.2 pulse gobbler the pulse gobbler on the scl pin is automatically adjusted to suppress spikes < 10 ns during hs mode. figure 6-10: hs mode sequence. s a ?0 0 0 0 1 x x x?b sr a ?slave address? a /a ?data? p s = start bit sr = repeated start bit a = acknowledge bit a = not acknowledge bit r/w = read/write bit r/w p = stop bit (stop condition terminates hs mode) f/s-mode hs-mode hs-mode continues f/s-mode sr a ?slave address? r/w hs select byte control byte command/data byte(s) control byte
mcp444x/446x ds22265a-page 58 ? 2010 microchip technology inc. 6.2.7 general call the general call is a method that the ?master? device can communicate with all other ?slave? devices. in a multi-master application, the other master devices are operating in slave mode. the general call address has two documented formats. these are shown in figure 6-11 . we have added a mcp44xx format in this figure as well. this will allow customers to have multiple i 2 c digital potentiometers on the bus and have them operate in a synchronous fashion (analogous to the dac sync pin functionality). if these mcp44xx 7-bit commands conflict with other i 2 c devices on the bus, then the customer will need two i 2 c busses and ensure that the devices are on the correct bus for their desired application functionality. dual pot devices can not update both pot0 and pot1 from a single command. to address this, there are general call commands for the wiper 0, wiper 1, and the tcon registers. table 6-3 shows the general call commands. three commands are specified by the i 2 c specification and are not applicable to the mcp44xx (so command is not acknowledged) the mcp44xx general call commands are acknowledge. any other command is not acknowledged. table 6-3: general call commands note: only one general call command per issue of the general call control byte. any additional general call commands are ignored and not acknowledged. 7-bit command (1, 2, 3) comment ?1000 00d?b write next byte (third byte) to volatile wiper 0 register ?1001 00d?b write next byte (third byte) to volatile wiper 1 register ?1100 00d?b write next byte (third byte) to tcon register ?1000 010?b or ?1000 011?b increment wiper 0 register ?1001 010?b or ?1001 011?b increment wiper 1 register ?1000 100?b or ?1000 101?b decrement wiper 0 register ?1001 100?b or ?1001 101?b decrement wiper 1 register note 1: any other code is not acknowledged. these codes may be used by other devices on the i 2 c bus. 2: the 7-bit command always appends a ?0? to form 8-bits. 3: ?d? is the d8 bit for the 9-bit write value.
? 2010 microchip technology inc. ds22265a-page 59 mcp444x/446x figure 6-11: general call formats. 0 000 s 0000 x xxxx a xx0ap general call address second byte ?7-bit command? reserved 7-bit commands (by i 2 c specification - philips # 9398 393 40011, ver. 2.1 january 2000) ?0000 011? b - reset and write programmable part of slave address by hardware. ?0000 010? b - write programmable part of slave address by hardware. ?0000 000? b - not allowed mcp44xx 7-bit commands ?1000 01x? b - increment wiper 0 register. ?1001 01x? b - increment wiper 1 register. the following is a microchip extension to this general call format 0 000 s 0000 x xxxx axd0a general call address second byte ?7-bit command? mcp44xx 7-bit commands ?1000 00d? b - write next byte (third byte) to volatile wiper 0 register. ?1001 00d? b - write next byte (third byte) to volatile wiper 1 register. d dddd dddap third byte the following is a ?hardware general call? format 0 000 s0000 x xxxx a xx1a general call address second byte ?7-bit command? x xxxx xxxap n occurrences of (data + a) this indicates a ?hardware general call? mcp44xx will ignore this byte and all following bytes (and a ), until ? 1000 10x? b - decrement wiper 0 register. ?1001 10x? b - decrement wiper 1 register. ?1100 00d? b - write next byte (third byte) to tcon register. a stop bit (p) is encountered. ?0? for general call command
mcp444x/446x ds22265a-page 60 ? 2010 microchip technology inc. notes:
? 2010 microchip technology inc. ds22265a-page 61 mcp444x/446x 7.0 device commands the mcp44xx?s i 2 c command formats are specified in this section. the i 2 c protocol does not specify how commands are formatted. the mcp44xx supports four basic commands. the location accessed determines the commands that are supported. for the volatile wiper registers, these commands are: ? write data ? read data ?increment data ?decrement data for the nonvolatile wiper eeprom, general purpose data eeprom, and the tcon register, these commands are: ? write data ? read data these commands have formats for both a single command or continuous commands. these commands are shown in tab l e 7 - 1 . each command has two operational states. the operational state determines if the device commands control the special features (write protect and wiperlock technology). these operational states are referred to as: ? normal serial commands ? high-voltage serial commands table 7-1: i 2 c commands normal serial commands are those where the hvc pin is driven to v ih or v il . with high-voltage serial commands, the hvc pin is driven to v ihh . in each mode, there are four possible commands. additionally, there are two commands used to enable or disable the special features (write protect and wiper lock technology) of the device. the commands are special cases of the increment and decrement high-voltage serial command. table 7-2 shows the supported commands for each memory location. table 7-3 shows an overview of all the device commands and their interaction with other device features. 7.1 command byte the mcp44xx?s command byte has three fields: the address, the command operation, and 2 data bits (see figure 7-1 ). currently only one of the data bits is defined (d8). the device memory is accessed when the master sends a proper command byte to select the desired operation. the memory location getting accessed is contained in the command byte?s ad3:ad0 bits. the action desired is contained in the command byte?s c1:c0 bits, see figure 7-1 . c1:c0 determines if the desired memory location will be read, written, incremented (wiper setting +1) or decremented (wiper setting -1). the increment and decrement commands are only valid on the volatile wiper registers, and in high voltage commands to enable/disable wiperlock technology and software write protect. if the address bits and command bits are not a valid combination, then the mcp44xx will generate a not acknowledge pulse to indicate the invalid combination. the i 2 c master device must then force a start condition to reset the mcp44xx?s i 2 c module. d9 and d8 are the most significant bits for the digital potentiometer?s wiper setting. the 8-bit devices utilize d8 as their msb while the 7-bit devices utilize d7 (from the data byte) as their msb. figure 7-1: command byte format. command # of bit clocks (1) operates on volatile/ nonvolatile memory operation mode write data single 29 both continuous 18n + 11 volatile only read data single 29 both random 48 both continuous 18n + 11 both (2) increment (3) single 20 volatile only continuous 9n + 11 volatile only decrement (3) single 20 volatile only continuous 9n + 11 volatile only note 1: ?n? indicates the number of times the command operation is to be repeated. 2: this command is useful to determine if a nonvolatile memory write cycle has completed. 3: high voltage increment and decrement commands on select nonvolatile memory locations enable/disable wiperlock technology and the software write protect feature. aa d 3 a d 2 a d 1 a d 0 c 1 c 0 d 9 d 8 a mcp4xxx command byte 00 = write data 01 = increment msbits (data) 10 = decrement 11 = read data command operation bits memory address
mcp444x/446x ds22265a-page 62 ? 2010 microchip technology inc. table 7-2: memory map and the supported commands address command data (10-bits) (1) comment value function 00h volatile wiper 0 write data nn nnnn nnnn read data ( 3 ) nn nnnn nnnn increment wiper ? decrement wiper ? 01h volatile wiper 1 write data nn nnnn nnnn read data ( 3 ) nn nnnn nnnn increment wiper ? decrement wiper ? 02h nv wiper 0 write data nn nnnn nnnn read data ( 3 ) nn nnnn nnnn high voltage increment ? wiper lock 0 disable ( 4 ) high voltage decrement ? wiper lock 0 enable ( 5 ) 03h nv wiper 1 write data nn nnnn nnnn read data ( 3 ) nn nnnn nnnn high voltage increment ? wiper lock 1 disable ( 4 ) high voltage decrement ? wiper lock 1 enable ( 5 ) 04h (2) volatile tcon 0 register write data nn nnnn nnnn read data ( 3 ) nn nnnn nnnn 05h (2) status register read data ( 3 ) nn nnnn nnnn 06h volatile wiper 2 write data nn nnnn nnnn read data ( 3 ) nn nnnn nnnn increment wiper ? decrement wiper ? 07h volatile wiper 3 write data nn nnnn nnnn read data ( 3 ) nn nnnn nnnn increment wiper ? decrement wiper ? 08h nv wiper 2 write data nn nnnn nnnn read data ( 3 ) nn nnnn nnnn high voltage increment ? wiper lock 2 disable ( 4 ) high voltage decrement ? wiper lock 2 enable ( 5 ) 09h nv wiper 3 write data nn nnnn nnnn read data ( 3 ) nn nnnn nnnn high voltage increment ? wiper lock 3 disable ( 4 ) high voltage decrement ? wiper lock 3 enable ( 5 ) 0ah (2) volatile tcon 1 register write data nn nnnn nnnn read data ( 3 ) nn nnnn nnnn 0bh (2) data eeprom write data nn nnnn nnnn read data ( 3 ) nn nnnn nnnn 0ch (2) data eeprom write data nn nnnn nnnn read data ( 3 ) nn nnnn nnnn 0dh (2) data eeprom write data nn nnnn nnnn read data ( 3 ) nn nnnn nnnn 0eh (2) data eeprom write data nn nnnn nnnn read data ( 3 ) nn nnnn nnnn 0fh data eeprom write data nn nnnn nnnn read data ( 3 ) nn nnnn nnnn high voltage increment ? write protect disable ( 4 ) high voltage decrement ? write protect enable ( 5 ) note 1: the data memory is only 9-bits wide, so the msb is ignored by the device. 2: increment or decrement commands are invalid for these addresses. 3: i 2 c read operation will read 2 bytes, of which the 10-bits of data are contained within. 4: disables wiperlock technology for wiper 0, wiper 1, wiper 2, wiper3, or disables write protect. 5: enables wiperlock technology for wiper 0, wiper 1, wiper 2, wiper3, or enables write protect.
? 2010 microchip technology inc. ds22265a-page 63 mcp444x/446x 7.2 data byte only the read command and the write command have data byte(s). the write command concatenates the 8 bits of the data byte with the one data bit (d8) contained in the command byte to form 9 bits of data (d8:d0). the command byte format supports up to 9 bits of data so that the 8-bit resistor network can be set to full-scale (100h or greater). this allows wiper connections to terminal a and to terminal b. the d9 bit is currently unused. 7.3 error condition if the four address bits received (ad3:ad0) and the two command bits received (c1:c0) are a valid combination, the mcp44xx will acknowledge the i 2 c bus. if the address bits and command bits are an invalid combination, then the mcp44xx will not acknowledge the i 2 c bus. once an error condition has occurred, any following commands are ignored until the i 2 c bus is reset with a start condition. 7.3.1 aborting a transmission a restart or stop condition in the expected data bit position will abort the current command sequence and data will not be written to the mcp44xx. table 7-3: commands command name writes value in eeprom operates on volatile/ nonvolatile memory high voltage (v ihh ) on hvc pin? impact on wiperlock or write protect works when wiper is ?locked?? write data yes (1) both ? unlocked (1) no read data ? both ? unlocked (1) no increment wiper ? volatile only ? unlocked (1) no decrement wiper ? volatile only ? unlocked (1) no high voltage write data yes both yes unchanged no high voltage read data ? both yes unchanged yes high voltage increment wiper ? volatile only yes unchanged no high voltage decrement wiper ? volatile only yes unchanged no modify write protect or wiperlock technology (high voltage) - enable ? (2) nonvolatile only (2) yes locked/ protected (2) yes modify write protect or wiperlock technology (high voltage) - disable ? (3) nonvolatile only (3) yes unlocked/ unprotected (3) yes note 1: this command will only complete, if wiper is ?unlocked? (wiperlock technology is disabled). 2: if the command is executed using address 02h, 03h 08h, or 09h; that corresponding wiper is locked or if with address 0fh, then write protect is enabled. 3: if the command is executed using with address 02h, 03h 08h, or 09h; that corresponding wiper is unlocked or if with address 0fh, then write protect is disabled.
mcp444x/446x ds22265a-page 64 ? 2010 microchip technology inc. 7.4 write data normal and high voltage the write command can be issued to both the volatile and nonvolatile memory locations. the format of the command, see figure 7-2 , includes the i 2 c control byte, an a bit, the mcp44xx command byte, an a bit, the mcp44xx data byte, an a bit, and a stop (or restart) condition. the mcp44xx generates the a / a bits. a write command to a volatile memory location changes that location after a properly formatted write command and the a / a clock have been received. a write command to a nonvolatile memory location will only start a write cycle after a properly formatted write command have been received and the stop condition has occurred. 7.4.1 single write to volatile memory for volatile memory locations, data is written to the mcp44xx after every byte transfer (during the acknowledge). if a stop or restart condition is generated during a data transfer (before the a), the data will not be written to the mcp44xx. after the a bit, the master can initiate the next sequence with a stop or restart condition. refer to figure 7-2 for the byte write sequence. 7.4.2 single write to nonvolatile memory the sequence to write to a single nonvolatile memory location is the same as a single write to volatile memory with the exception that the eeprom write cycle (t wc ) is started after a properly formatted command, including the stop bit, is received. after the stop condition occurs, the serial interface may immediately be re-enabled by initiating a start condition. during an eeprom write cycle, access to the volatile memory (addresses 00h, 01h, 04h, 05h, 06h, 07h, and 0ah) is allowed when using the appropriate command sequence. commands that address nonvolatile memory are ignored until the eeprom write cycle (t wc ) completes. this allows the host controller to operate on the volatile wiper registers, the tcon register, and to read the status register. the eewa bit in the status register indicates the status of an eeprom write cycle. once a write command to a nonvolatile memory location has been received, no other commands should be received before the stop condition occurs. figure 7-2 shows the waveform for a single write. 7.4.3 continuous writes to volatile memory a continuous write mode of operation is possible when writing to the volatile memory registers (address 00h, 01h, 04h, 06h, 07h, and 0ah). this continuous write mode allows writes without a stop or restart condition or repeated transmissions of the i 2 c control byte. figure 7-3 shows the sequence for three continuous writes. the writes do not need to be to the same volatile memory address. the sequence ends with the master sending a stop or restart condition. 7.4.4 continuous writes to nonvolatile memory if a continuous write is attempted on nonvolatile memory, the missing stop condition will cause the command to be an error condition (a ). a start bit is required to reset the command state machine. 7.4.5 the high voltage command (hvc) signal the high voltage command (hvc) signal is multiplexed with address 0 (a0) and is used to indicate that the command, or sequence of commands, are in the high voltage operational state. high voltage commands allow the device?s wiperlock technology and write protect features to be enabled and disabled. the hvc pin has an internal resistor connection to the mcp44xxs internal v dd signal. note: writes to certain memory locations will be dependant on the state of the wiperlock technology bits and the write protect bit.
? 2010 microchip technology inc. ds22265a-page 65 mcp444x/446x figure 7-2: i 2 c write sequence. figure 7-3: i 2 c continuous volatile wiper write. control byte write command write data bits 1 010 s 1 a1 a0 0 0 ad ad ad ad a0xd8ad3 d7 d6 d5 d4 d2 d1 d0 a p 0 1 2 3 fixed address variable address device memory address command write ?data? bits write bit stop bit control byte write command write data bits 1 010 s 1 a1 a0 0 0 a0xd8ad3 d7 d6 d5 d4 d2 d1 d0 a fixed address variable address device memory address command write ?data? bits write command write data bits 00xd8a d3 d7 d6 d5 d4 d2 d1 d0 a write command write data bits 00xd8a d3 d7 d6 d5 d4 d2 d1 d0 a p write bit ad ad ad ad 0 1 2 3 ad ad ad ad 0 1 2 3 ad ad ad ad 0 1 2 3 note: only functions when writing the volatile wiper registers (ad3:ad0 = 00h, 01h, 06h, and 07h) or the tcon registers (ad3:ad0 = 04h and 0ah)
mcp444x/446x ds22265a-page 66 ? 2010 microchip technology inc. 7.5 read data normal and high voltage the read command can be issued to both the volatile and nonvolatile memory locations. the format of the command (see figure 7-4 ), includes the start condi- tion, i 2 c control byte (with r/w bit set to ?0?), a bit, mcp44xx command byte, a bit, followed by a repeated start bit, i 2 c control byte (with r/w bit set to ?1?), and the mcp44xx transmitting the requested data high byte, and a bit, the data low byte, the master generating the a , and stop condition. the i 2 c control byte requires the r/w bit equal to a logic one (r/w = 1) to generate a read sequence. the memory location read will be the last address contained in a valid write mcp44xx command byte or address 00h if no write operations have occurred since the device was reset (power-on reset or brown-out reset). during a write cycle (write or high voltage write to a nonvolatile memory location) the read command can only read the volatile memory locations. by reading the status register (05h), the host controller can determine when the write cycle has completed (via the state of the eewa bit). read operations initially include the same address byte sequence as the write sequence (shown in figure 6-9 ). this sequence is followed by another control byte (including the start condition and acknowledge) with the r/w bit equal to a logic one (r/w = 1) to indicate a read. the mcp44xx will then transmit the data contained in the addressed register. this is followed by the master generating an a bit in preparation for more data, or an a bit followed by a stop. the sequence is ended with the master generating a stop or restart condition. the internal address pointer is maintained. if this address pointer is for a nonvolatile memory address and the read control byte addresses the device during a nonvolatile write cycle (t wc ) the device will respond with an a bit. 7.5.1 single read figure 7-4 show the waveforms for a single read. for single reads the master sends a stop or restart condition after the data byte is sent from the slave. 7.5.1.1 random read figure 7-5 shows the sequence for a random reads. refer to figure 7-5 for the random byte read sequence. 7.5.2 continuous reads continuous reads allows the devices memory to be read quickly. continuous reads are possible to all memory locations. if a nonvolatile memory write cycle is occurring, then read commands may only access the volatile memory locations. figure 7-6 shows the sequence for three continuous reads. for continuous reads , instead of transmitting a stop or restart condition after the data transfer, the master reads the next data byte. the sequence ends with the master not acknowledging and then sending a stop or restart. 7.5.3 the high voltage command (hvc) signal the high voltage command (hvc) signal is multiplexed with address 0 (a0) and is used to indicate that the command, or sequence of commands, are in the high voltage mode. high voltage commands allow the device?s wiperlock technology and write protect features to be enabled and disabled. the hvc pin has an internal resistor connection to the mcp44xx?s internal v dd signal. 7.5.4 ignoring an i 2 c transmission and ?falling off? the bus the mcp44xx expects to receive complete, valid i 2 c commands and will assume any command not defined as a valid command is due to a bus corruption and will enter a passive high condition on the sda signal. all signals will be ignored until the next valid start condition and control byte are received.
? 2010 microchip technology inc. ds22265a-page 67 mcp444x/446x figure 7-4: i 2 c read (last memory address accessed). figure 7-5: i 2 c random read. stop bit control byte 1 010 s 1 a1 a0 1 a fixed address variable address read bits p 0 000 0 0 0d8a 1 read bit d3 d7 d6 d5 d4 d2 d1 d0 a 2 read data bits note 1: master device is responsible for a / a signal. if a a signal occurs, the mcp44xx will abort this transfer and release the bus. 2: the master device will not acknowledge, and the mcp44xx will release the bus so the master device can generate a stop or repeated start condition. 3: the mcp44xx retains the last ?device memory address? that it has received. this is the mcp44xx does not ?corrupt? the ?device memory address? after repeated start or stop conditions. 4: the device memory address pointer defaults to 00h on por and bor conditions. stop bit control byte read command 1 010 s 1 a1 a0 0 1 ad ad ad ad a1xxasr 0 1 2 3 fixed address variable address device memory address command control byte read bits p 0 000 0 0 0d8a 1 write bit d3 d7 d6 d5 d4 d2 d1 d0 a 2 1 0 1 0 1 a1 a0 1 a read bit repeated start bit read data bits note 1: master device is responsible for a / a signal. if a a signal occurs, the mcp44xx will abort this transfer and release the bus. 2: the master device will not acknowledge, and the mcp44xx will release the bus so the mas- ter device can generate a stop or repeated start condition. 3: the mcp44xx retains the last ?device memory address? that it has received. this is the mcp44xx does not ?corrupt? the ?device memory address? after repeated start or stop conditions.
mcp444x/446x ds22265a-page 68 ? 2010 microchip technology inc. figure 7-6: i 2 c continuos reads. stop bit control byte 1 010 s 1 a1 a0 1 a fixed address variable address read bits 0 000 0 0 0d8a 1 read bit d3 d7 d6 d5 d4 d2 d1 d0 a 1 read data bits 0 000 0 0 0d8a 1 d3 d7 d6 d5 d4 d2 d1 d0 a 1 p 0 000 0 0 0d8a 1 d3 d7 d6 d5 d4 d2 d1 d0 a 2 read data bits read data bits note 1: master device is responsible for a / a signal. if a a signal occurs, the mcp44xx will abort this transfer and release the bus. 2: the master device will not acknowledge, and the mcp44xx will release the bus so the master device can generate a stop or repeated start condition.
? 2010 microchip technology inc. ds22265a-page 69 mcp444x/446x 7.6 increment wiper normal and high voltage the increment command provides a quick and easy method to modify the potentiometer?s wiper by +1 with minimal overhead. the increment command will only function on the volatile wiper setting memory locations 00h, 01h, 06h and 07h. the increment command to nonvolatile addresses will be ignored and will generate a a . when executing an increment command, the volatile wiper setting will be altered from n to n+1 for each increment command received. the value will increment up to 100h max on 8-bit devices and 80h on 7-bit devices. if multiple increment commands are received after the value has reached 100h (or 80h), the value will not be incremented further. tab le 7 -4 shows the increment command versus the current volatile wiper value. the increment command will most commonly be performed on the volatile wiper locations until a desired condition is met. the value in the volatile wiper register would need to be read using a read operation in order to write the new setting to the corresponding nonvolatile wiper memory using a write operation. the mcp44xx is responsible for generating the a bits. refer to figure 7-7 for the increment command sequence. the sequence is terminated by the stop condition. so when executing a continuous command string, the increment command can be followed by any other valid command. this means that writes do not need to be to the same volatile memory address. the advantage of using an increment command instead of a read-modify-write series of commands is speed and simplicity. the wiper will transition after each command acknowledge when accessing the volatile wiper registers. table 7-4: increment operation vs. volatile wiper value 7.6.1 the high voltage command (hvc) signal the high voltage command (hvc) signal is multiplexed with address 0 (a0) and is used to indicate that the command, or sequence of commands, are in the high voltage mode. signals > v ihh (~8.5v) on the hvc/a0 pin puts mcp44xx devices into high voltage mode. high voltage commands allow the device?s wiperlock technology and write protect features to be enabled and disabled. the hvc pin has an internal resistor connection to the mcp44xx?s internal v dd signal. figure 7-7: i 2 c increment command sequence. note: table 7-4 shows the valid addresses for the increment wiper command. other addresses are invalid. note: the command sequence can go from an increment to any other valid command for the specified address. issuing an increment or decrement to a nonvolatile location will cause an error condition (a will be generated). current wiper setting wiper (w) properties increment command operates? 7-bit pot 8-bit pot 3ffh 081h 3ffh 101h reserved (full-scale (w = a)) no 080h 100h full-scale (w = a) no 07fh 041h 0ffh 081 w = n 040h 080h w = n (mid-scale) yes 03fh 001h 07fh 001 w = n 000h 000h zero scale (w = b) yes note: there is a required delay after the hvc pin is driven to the v ihh level to the 1st edge of the scl pin. control byte incr command (n+1) incr command (n+2) 1 010 s 1 a1 a0 0 0 ad ad ad ad a1xxa0 ad ad ad ad 1x x ap (2) 0 1 2 3 4321 fixed address variable address device memory address command write bit note1: increment command (incr) only functions when accessing the volatile wiper registers (ad3:ad0 = 00h, 01h, 06h, and 07h). 2: this command sequence does not need to terminate (using the stop bit) and can change to any other desired command sequence (increment, read, or write).
mcp444x/446x ds22265a-page 70 ? 2010 microchip technology inc. 7.7 decrement wiper normal and high voltage the decrement command provides a quick and easy method to modify the potentiometer?s wiper by -1 with minimal overhead. the decrement command will only function on the volatile wiper setting memory locations 00h and 01h. decrement commands to nonvolatile addresses will be ignored and will generate an a bit. when executing a decrement command, the volatile wiper setting will be altered from n to n-1 for each decrement command received. the value will decrement down to 000h min. if multiple decrement commands are received after the value has reached 000h, the value will not be decremented further. table 7-5 shows the increment command versus the current volatile wiper value. the decrement command will most commonly be performed on the volatile wiper locations until a desired condition is met. the value in the volatile wiper register would need to be read using a read operation in order to write the new setting to the corresponding nonvolatile wiper memory using a write operation. the mcp44xx is responsible for generating the a bits. refer to figure 7-8 for the decrement command sequence. the sequence is terminated by the stop condition. so when executing a continuous command string, the increment command can be followed by any other valid command. this means that writes do not need to be to the same volatile memory address. the advantage of using a decrement command instead of a read-modify-write series of commands is speed and simplicity. the wiper will transition after each command acknowledge when accessing the volatile wiper registers. table 7-5: decrement operation vs. volatile wiper value 7.7.1 the high voltage command (hvc) signal the high voltage command (hvc) signal is multiplexed with address 0 (a0) and is used to indicate that the command, or sequence of commands, are in the high voltage mode. signals > v ihh (~8.5v) on the hvc/a0 pin puts mcp44xx devices into high voltage mode. high voltage commands allow the device?s wiperlock technology and write protect features to be enabled and disabled. the hvc pin has an internal resistor connection to the mcp44xx?s internal v dd signal. figure 7-8: i 2 c decrement command sequence. note: table 7-5 shows the valid addresses for the decrement wiper command. other addresses are invalid. note: the command sequence can go from an increment to any other valid command for the specified address. issuing an increment or decrement to a nonvolatile location will cause an error condition (a will be generated). current wiper setting wiper (w) properties decrement command operates? 7-bit pot 8-bit pot 3ffh 081h 3ffh 101h reserved (full-scale (w = a)) no 080h 100h full-scale (w = a) yes 07fh 041h 0ffh 081 w = n 040h 080h w = n (mid-scale) yes 03fh 001h 07fh 001 w = n 000h 000h zero scale (w = b) no note: there is a required delay after the hvc pin is driven to the v ihh level to the 1st edge of the scl pin. control byte decr command (n-1) decr command (n-2) 1 010 s1a1a00 1 ad ad ad ad a0xxa1 ad ad ad ad 0x xap (2) 0 1 2 3 4321 fixed address variable address device memory address command write bit note1: decrement command (decr) only functions when accessing the volatile wiper registers (ad3:ad0 = 00h, 01h, 06h, and 07h). 2: this command sequence does not need to terminate (using the stop bit) and can change to any other desired command sequence (incr, read, or write).
? 2010 microchip technology inc. ds22265a-page 71 mcp444x/446x 7.8 modify write protect or wiperlock technology (high voltage) enable and disable these commands are special cases of the high voltage decrement wiper and the high voltage increment wiper commands to the nonvolatile memory locations 02h, 03h, 08h, 09h, and 0fh. this command is used to enable or disable either the software write protect, wiper 0 wiperlock technology, wiper 1 wiperlock technology, wiper 2 wiperlock technology, or wiper 3 wiperlock technology. ta bl e 7 - 6 shows the memory addresses, the high voltage command and the result of those commands on the nonvolatile wp, wl0, or wl1 bits. 7.8.1 single modify (enable or disable) write protect or wiperlock technology (high voltage) figure 7-9 (disable) and figure 7-10 (enable) show the formats for a single modify write protect or wiper-lock technology command. a modify write protect or wiperlock technology command will only start an eeprom write cycle (t wc ) after a properly formatted command has been received and the stop condition occurs. during an eeprom write cycle, only serial commands to volatile memory (addresses 00h, 01h, 04h, and 05h) are accepted. all other serial commands are ignored until the eeprom write cycle (t wc ) completes. this allows the host controller to operate on the volatile wiper registers and the tcon register, and to read the status register. the eewa bit in the status register indicates the status of an eeprom write cycle. table 7-6: address map to modify write protect and wiperlock technology memory address commands and results high voltage decrement wiper high voltage increment wiper 00h wiper 0 register is decremented wiper 0 register is incremented 01h wiper 1 register is decremented wiper 1 register is incremented 02h wl0 is enabled wl0 is disabled 03h wl1 is enabled wl1 is disabled 04h (1) tcon0 register not changed tcon0 register not changed 05h (1) status register not changed status register not changed 06h wiper 2 register is decremented wiper 2 register is incremented 07h wiper 3 register is decremented wiper 3 register is incremented 08h wl2 is enabled wl2 is disabled 09h wl3 is enabled wl3 is disabled 0ah (1) tcon1 register not changed tcon1 register not changed 0bh - 0eh (1) reserved reserved 0fh wp is enabled wp is disabled note 1: reserved addresses: increment or decrement commands are invalid for these addresses.
mcp444x/446x ds22265a-page 72 ? 2010 microchip technology inc. figure 7-9: i 2 c disable command sequence. figure 7-10: i 2 c enable command sequence. control byte disable command 1 010 s 1 a1 a0 0 0 ad ad ad ad a1xxa p 1 2 3 fixed address variable address device memory address command (increment) write bit 0 control byte enable command 1 010 s 1 a1 a0 0 1 ad ad ad ad a0xxa p 0 1 2 3 fixed address variable address device memory address command (decrement) write bit
? 2010 microchip technology inc. ds22265a-page 73 mcp444x/446x 8.0 applications examples nonvolatile digital potentiometers have a multitude of practical uses in modern electronic circuits. the most popular uses include precision calibration of set point thresholds, sensor trimming, lcd bias trimming, audio attenuation, adjustable power supplies, motor control overcurrent trip setting, adjustable gain amplifiers and offset trimming. the mcp44xx devices can be used to replace the common mechanical trim pot in applications where the operating and terminal voltages are within cmos process limitations (v dd = 2.7v to 5.5v). 8.1 techniques to force the hvc/a0 pin to v ihh the circuit in figure 8-1 shows a method using the tc1240a doubling charge pump. when the shdn pin is high, the tc1240a is off, and the level on the hvc/ a0 pin is controlled by the pic? microcontrollers (mcus) io2 pin. when the shdn pin is low, the tc1240a is on and the v out voltage is 2 * v dd . the resistor r 1 allows the hvc/a0 pin to go higher than the voltage such that the pic mcu?s io2 pin ?clamps? at approximately v dd . figure 8-1: using the tc1240a to generate the v ihh voltage. the circuit in figure 8-2 shows the method used on the mcp402x nonvolatile digital potentiometer evaluation board (part number: mcp402xev). this method requires that the system voltage be approximately 5v. this ensures that when the pic10f206 enters a brown- out condition, there is an insufficient voltage level on the hvc/a0 pin to change the stored value of the wiper. the mcp402x nonvolatile digital potentiometer eval- uation board user?s guide (ds51546) contains a complete schematic. gp0 is a general purpose i/o pin, while gp2 can either be a general purpose i/o pin or it can output the internal clock. for the serial commands, configure the gp2 pin as an input (high impedance). the output state of the gp0 pin will determine the voltage on the hvc/a0 pin (v il or v ih ). for high-voltage serial commands, force the gp0 output pin to output a high level (v oh ) and configure the gp2 pin to output the internal clock. this will form a charge pump and increase the voltage on the cs pin (when the system voltage is approximately 5v). figure 8-2: mcp4xxx nonvolatile digital potentiometer evaluation board (mcp402xev) implementation to generate the v ihh voltage. hvc/a0 pic mcu mcp4xxx r 1 io1 io2 c 2 tc1240a v in shdn c+ c- v out c 1 hvc/a0 pic10f206 mcp4xxx r 1 gp0 gp2 c 2 c 1
mcp444x/446x ds22265a-page 74 ? 2010 microchip technology inc. 8.2 using shutdown modes figure 8-3 shows a possible application circuit where the independent terminals could be used. disconnecting the wiper allows the transistor input to be taken to the bias voltage level (disconnecting a and or b may be desired to reduce system current). disconnecting terminal a modifies the transistor input by the r bw rheostat value to the common b. disconnecting terminal b modifies the transistor input by the r aw rheostat value to the common a. the common a and common b connections could be connected to v dd and v ss . figure 8-3: example application circuit using terminal disconnects. 8.3 software reset sequence at times, it may become necessary to perform a software reset sequence to ensure the mcp44xx device is in a correct and known i 2 c interface state. this technique only resets the i 2 c state machine. this is useful if the mcp44xx device powers up in an incorrect state (due to excessive bus noise, etc), or if the master device is reset during communication. figure 8-4 shows the communication sequence to software reset the device. figure 8-4: software reset sequence format. the 1st start bit will cause the device to reset from a state in which it is expecting to receive data from the master device. in this mode, the device is monitoring the data bus in receive mode and can detect the start bit forces an internal reset. the nine bits of ?1? are used to force a reset of those devices that could not be reset by the previous start bit. this occurs only if the mcp44xx is driving an a bit on the i 2 c bus, or is in output mode (from a read command) and is driving a data bit of ?0? onto the i 2 c bus. in both of these cases, the previous start bit could not be generated due to the mcp44xx holding the bus low. by sending out nine ?1? bits, it is ensured that the device will see a a bit (the master device does not drive the i 2 c bus low to acknowledge the data sent by the mcp44xx), which also forces the mcp44xx to reset. the 2nd start bit is sent to address the rare possibility of an erroneous write. this could occur if the master device was reset while sending a write command to the mcp44xx, and then as the master device returns to normal operation and issues a start condition while the mcp44xx is issuing an acknowledge. in this case, if the 2nd start bit is not sent (and the stop bit was sent) the mcp44xx could initiate a write cycle. the stop bit terminates the current i 2 c bus activity. the mcp44xx waits to detect the next start condition. this sequence does not effect any other i 2 c devices which may be on the bus, as they should disregard this as an invalid command. balance bias w b input input to base of transistor (or amplifier) a common b common a note: this technique is documented in an1028. note: the potential for this erroneous write only occurs if the master device is reset while sending a write command to the mcp44xx. s ?1? ?1? ?1? ?1? ?1? ?1? ?1? ?1? s p start bit nine bits of ?1? start bit stop bit
? 2010 microchip technology inc. ds22265a-page 75 mcp444x/446x 8.4 using the general call command the use of the general call address increment, decrement, or write commands is analogous to the ?load? feature (ldac pin) on some dacs (such as the mcp4921). this allows all the devices to ?update? the output level ?at the same time?. for some applications, the ability to update the wiper values ?at the same time? may be a requirement, since they delay from writing to one wiper value and then the next may cause application issues. a possible example would be a ?tuned? circuit that uses several mcp44xx in rheostat configuration. as the system condition changes (temperature, load, etc.) these devices need to be changed (incremented/decremented) to adjust for the system change. these changes will either be in the same direction or in opposite directions. with the potentiometer device, the customer can either select the pxb terminals (same direction) or the pxa terminal(s) (opposite direction). figure 8-6 shows that the update of six devices takes 6*t i2cdly time in ?normal? operation, but only 1*t i2cdly time in ?general call? operation. figure 8-5 shows two i 2 c bus configurations. in many cases, the single i 2 c bus configuration will be adequate. for applications that do not want all the mcp44xx devices to do general call support or have a conflict with general call commands, the multiple i 2 c bus configuration would be used. figure 8-5: typical application i 2 c bus configurations. figure 8-6: example comparison of ?normal operation? vs. ?general call operation? wiper updates. note: the application system may need to partition the i 2 c bus into multiple busses to ensure that the mcp44xx general call commands do not conflict with the general call commands that the other i 2 c devices may have defined. also if only a portion of the mcp44xx devices are to require this synchronous operation, then the devices that should not receive these commands should be on the second i 2 c bus. single i 2 c bus configuration host controller device 1 device 3 device n device 2 device 4 multiple i 2 c bus configuration host controller device 1a device 3a device na device 2a device 4a device 1b device 3b device nb device 2b device 4b bus b bus a device 1n device 3n device nn device 2n device 4n bus n normal operation general call operation inc pot01 inc pot02 inc pot03 inc pot04 inc pot05 inc pot06 t i2cdly t i2cdly t i2cdly t i2cdly t i2cdly t i2cdly = time from one i 2 c command completed to completing the next i 2 c command. inc pots 01-06 inc pots 01-06 inc pots 01-06 inc pots 01-06 inc pots 01-06 inc pots 01-06 t i2cdly t i2cdly t i2cdly t i2cdly t i2cdly t i2cdly t i2cdly
mcp444x/446x ds22265a-page 76 ? 2010 microchip technology inc. 8.5 implementing log steps with a linear digital potentiometer in audio volume control applications, the use of logarithmic steps is desirable since the human ear hears in a logarithmic manner. the use of a linear potentiometer can approximate a log potentiometer, but with fewer steps. an 8-bit potentiometer can achieve fourteen 3 db log steps plus a 100% (0 db) and a mute setting. figure 8-7 shows a block diagram of one of the mcp44x1 resistor networks being used to attenuate an input signal. in this case, the attenuation will be ground referenced. terminal b can be connected to a common mode voltage, but the voltages on the a, b and wiper terminals must not exceed the mcp44x1?s v dd /v ss voltage limits. figure 8-7: signal attenuation block diagram - ground referenced. equation 8-1 shows the equation to calculate voltage db gain ratios for the digital potentiometer, while equation 8-2 shows the equation to calculate resistance db gain ratios. these two equations assume that the b terminal is connected to ground. if terminal b is not directly resistively connected to ground, then this terminal b to ground resistance (r b2gnd ) must be included into the calculation. equation 8-3 shows this equation. equation 8-1: db calculations (voltage) equation 8-2: db calculations (resistance) - case 1 equation 8-3: db calculations (resistance) - case 2 table 8-1 shows the codes that can be used for 8-bit digital potentiometers to implement the log attenuation. the table shows the wiper codes for -3 db, -2 db, and -1 db attenuation steps. this table also shows the calculated attenuation based on the wiper code?s linear step. calculated attenuation values less than the desired attenuation are shown with red text. at lower wiper code values, the attenuation may skip a step, if this occurs the next attenuation value is colored magenta to highlight that a skip occurred. for example, in the -3 db column the -48 db value is highlighted since the -45 db step could not be implemented (there are no wiper codes between 2 and 1). p0a mcp44x1 p0w p0b l = 20 * log 10 (v out / v in ) db v out / v in ratio -3 0.70795 -2 -1 0.79433 0.89125 l = 20 * log 10 (r bw / r ab ) terminal b connected to ground (see figure 8-7 ) l = 20 * log 10 ( (r bw + r b2gnd ) / (r ab + r b2gnd ) ) terminal b through r b2gnd to ground
? 2010 microchip technology inc. ds22265a-page 77 mcp444x/446x table 8-1: linear to log attenuation for 8-bit digital potentiometers # of steps -3 db steps -2 db steps -1 db steps desired attenuation wiper code calculated attenuation (1) desired attenuation wiper code calculated attenuation (1) desired attenuation wiper code calculated attenuation (1) 0 0 db 256 0 db 0 db 256 0 db 0 db 256 0 db 1 -3 db 181 -3.011 db -2 db 203 -2.015 db -1 db 228 -1.006 db 2 -6 db 128 -6.021 db -4 db 162 -3.975 db -2 db 203 -2.015 db 3-9db91 -8.984 db -6 db 128 -6.021 db -3 db 181 -3.011 db 4 -12 db 64 -12.041 db -8 db 102 -7.993 db -4 db 162 -3.975 db 5 -15 db 46 -14.910 db -10 db 81 -9.995 db -5 db 144 -4.998 db 6 -18 db 32 -18.062 db -12 db 64 -12.041 db -6 db 128 -6.021 db 7 -21 db 23 -20.930 db -14 db 51 -14.013 db -7 db 114 -7.027 db 8 -24 db 16 -24.082 db -16 db 41 -15.909 db -8 db 102 -7.993 db 9 -27 db 11 -27.337 db -18 db 32 -18.062 db -9 db 91 -8.984 db 10 -30 db 8 -30.103 db -20 db 26 -19.865 db -10 db 81 -9.995 db 11 -33 db 6 -32.602 db -22 db 20 -22.144 db -11 db 72 -11.018 db 12 -36 db 4 -36.124 db -24 db 16 -24.082 db -12 db 64 -12.041 db 13 -39 db 3 -38.622 db -26 db 13 -25.886 db -13 db 57 -13.047 db 14 -42 db 2 -42.144 db -28 db 10 -28.165 db -14 db 51 -14.013 db 15 -48 db 1 -48.165 db -30 db 8 -30.103 db -15 db 46 - 14.910 db 16 mute 0 mute -32 db 6 -32.602 db -16 db 41 -15.909 db 17 -34 db 5 -34.185 db -17 db 36 -17.039 db 18 -36 db 4 -36.124 db -18 db 32 -18.062 db 19 -38 db 3 -38.622 db -19 db 29 -18.917 db 20 -42 db 2 -42.144 db -20 db 26 -19.865 db 21 -48 db 1 -48.165 db -21 db 23 - 20.930 db 22 mute 0 mute -22 db 20 -22.144 db 23 -23 db 18 -23.059 db 24 -24 db 16 -24.082 db 25 -25 db 14 -25.242 db 26 -26 db 13 -25.886 db 27 -27db 11 -27.337 db 28 -28 db 10 -28.165 db 29 -29 db 9 -29.080 db 30 -30 db 8 -30.103 db 31 -31 db 7 -31.263 db 32 -33 db 6 -32.602 db 33 -34 db 5 -34.185 db 34 -36 db 4 -36.124 db 35 -39 db 3 -38.622 db 36 -42 db 2 -42.144 db 37 -48 db 1 -48.165 db 38 mute 0 mute note 1: attenuation values do not include errors from digital potentiometer errors, such as full scale error or zero scale error.
mcp444x/446x ds22265a-page 78 ? 2010 microchip technology inc. 8.6 design considerations in the design of a system with the mcp44xx devices, the following considerations should be taken into account: ? power supply considerations ? layout considerations 8.6.1 power supply considerations the typical application will require a bypass capacitor in order to filter high-frequency noise, which can be induced onto the power supply's traces. the bypass capacitor helps to minimize the effect of these noise sources on signal integrity. figure 8-8 illustrates an appropriate bypass strategy. in this example, the recommended bypass capacitor value is 0.1 f. this capacitor should be placed as close (within 4 mm) to the device power pin (v dd ) as possible. the power source supplying these devices should be as clean as possible. if the application circuit has separate digital and analog power supplies, v dd and v ss should reside on the analog plane. figure 8-8: typical microcontroller connections. 8.6.2 layout considerations several layout considerations may be applicable to your application. these may include: ? noise ? footprint compatibility ? pcb area requirements 8.6.2.1 noise inductively-coupled ac transients and digital switching noise can degrade the input and output signal integrity, potentially masking the mcp44xx?s performance. careful board layout minimizes these effects and increases the signal-to-noise ratio (snr). multi-layer boards utilizing a low-inductance ground plane, isolated inputs, isolated outputs and proper decoupling are critical to achieving the performance that the silicon is capable of providing. particularly harsh environments may require shielding of critical signals. if low noise is desired, breadboards and wire-wrapped boards are not recommended. 8.6.2.2 footprint compatibility the specification of the mcp44xx pinouts was done to allow systems to be designed to easily support the use of either the dual (mcp46xx) or quad (mcp44xx) device. figure 8-9 shows how the dual pinout devices fit on the quad device footprint. for the rheostat devices, the dual device is in the msop package, so the footprints would need to be offset from each other. figure 8-9: quad pinout (tssop package) vs. dual pinout. v dd v dd v ss v ss mcp444x/446x 0.1 f pic tm microcontroller 0.1 f scl hvc/a0 w b a sda a1 1 2 3 4 17 18 19 20 reset a1 wp v dd mcp44x1 quad potentiometers tssop 5 6 7 14 15 16 p0w p0b p0a p1a p1w p1b v ss hvc/a0 sda scl mcp44x2 quad rheostat 1 2 3 4 11 12 13 14 p0b a1 p0w v dd tssop 5 6 7 8 9 10 p2w p1w p2b p3b p3w p1b v ss hvc/a0 sda scl 8 9 10 p3b p3w p3a 12 12 p2w p2a p2b 11 mcp42x1 pinout (1) mcp42x2 pinout note 1: pin 15 (reset ) is the address a2 (a2) pin on the mcp46x1 device.
? 2010 microchip technology inc. ds22265a-page 79 mcp444x/446x figure 8-10 shows possible layout implementations for an application to support the quad and dual options on the same pcb. figure 8-10: layout to support quad and dual devices. 8.6.2.3 pcb area requirements in some applications, pcb area is a criteria for device selection. table 8-2 shows the package dimensions and area for the different package options. the table also shows the relative area factor compared to the smallest area. for space critical applications, the qfn package would be the suggested package. table 8-2: package footprint (1) 8.6.3 resistor tempco characterization curves of the resistor temperature coefficient (tempco) are shown in figure 2-10 , figure 2-26 , figure 2-41 , and figure 2-56 . these curves show that the resistor network is designed to correct for the change in resistance as temperature increases. this technique reduces the end to end change is r ab resistance. 8.6.4 high voltage tolerant pins high voltage support (v ihh ) on the serial interface pins supports two features. these are: ? in-circuit accommodation of split rail applications and power supply sync issues ? user configuration of the nonvolatile eeprom, write protect, and wiperlock feature potentiometers devices rheostat devices mcp44x1 mcp46x1 mcp44x2 mcp46x2 package package footprint pins type code dimensions (mm) area (mm 2 ) relative area xy 14 tssop st 5.10 6.40 32.64 2.04 20 qfn ml 4.00 4.00 16.00 1 tssop st 6.60 6.40 42.24 2.64 note 1: does not include recommended land pattern dimensions. note: in many applications, the high voltage will only be present at the manufacturing stage so as to ?lock? the nonvolatile wiper value (after calibration) and the contents of the eeprom. this ensures that since high voltage is not present under normal operating conditions, these values can not be modified.
mcp444x/446x ds22265a-page 80 ? 2010 microchip technology inc. 9.0 development support 9.1 development tools several development tools are available to assist in your design and evaluation of the mcp44xx devices. the currently available tools are shown in ta bl e 9 - 1 . these boards may be purchased directly from the microchip web site at www.microchip.com. 9.2 technical documentation several additional technical documents are available to assist you in your design and development. these technical documents include application notes, technical briefs, and design guides. ta bl e 9 - 2 shows some of these documents. table 9-1: development tools table 9-2: technical documentation board name part # supported devices 20-pin tssop and ssop evaluation board tssop20ev mcp44xx mcp46xx digital potentiometer pictail plus demo board (1, 2) mcp46xxdm-ptpls mcp46xx mcp46xx digital potentiometer evaluation board (2) mcp46xxev mcp46x1 note 1: requires a picdem demo board. see the user?s guide for additional information and requirements. 2: requires a pickit serial analyzer. see the user?s guide for additional information and requirements. application note number title literature # an1316 using digital potentiometers for programmable amplifier gain ds01316 an1080 understanding digital potentiometers resistor variations ds01080 an737 using digital potentiometers to design low-pass adjustable filters ds00737 an692 using a digital potentiometer to optimize a precision single supply photo detect ds00692 an691 optimizing the digital potentiometer in precision circuits ds00691 an219 comparing digital potentiometers to mechanical potentiometers ds00219 ? digital potentiometer design guide ds22017 ? signal chain design guide ds21825
? 2010 microchip technology inc. ds22265a-page 81 mcp444x/446x 10.0 packaging information 10.1 package marking information legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 14-lead tssop xxxxxxxx yyww nnn example 4462502e 1035 256 xxxxx 20-lead qfn (4x4) xxxxxx yywwnnn example xxxxxx 4461 502eml 256 ^^ 3 e 20-lead tssop xxxxxxxx xxxxx nnn example 1035 yyww 4461502 est 256 1035 ^^ 3 e
mcp444x/446x ds22265a-page 82 ? 2010 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2010 microchip technology inc. ds22265a-page 83 mcp444x/446x note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp444x/446x ds22265a-page 84 ? 2010 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2010 microchip technology inc. ds22265a-page 85 mcp444x/446x d exposed pad e e2 2 1 n top view note 1 n l k b e d2 2 1 a a1 a3 bottom view
mcp444x/446x ds22265a-page 86 ? 2010 microchip technology inc.
? 2010 microchip technology inc. ds22265a-page 87 mcp444x/446x d e e1 note 1 1 2 b e a a1 a2 c l1 l n
mcp444x/446x ds22265a-page 88 ? 2010 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2010 microchip technology inc. ds22265a-page 89 mcp444x/446x appendix a: revision history revision a (september 2010) ? original release of this document.
mcp444x/446x ds22265a-page 90 ? 2010 microchip technology inc. notes:
? 2010 microchip technology inc. ds22265a-page 91 mcp444x/446x appendix b: characterization data analysis some designers may want to understand the device operational characteristics outside of the specified operating conditions of the device. applications where the knowledge of the resistor network characteristics could be useful include battery powered devices and applications that experience brown-out conditions. in battery applications, the application voltage decays over time until new batteries are installed. as the voltage decays, the system will continue to operate. at some voltage level, the application will be below its specified operating voltage range. this is dependent on the individual components used in the design. it is still useful to understand the device characteristics to expect when this low-voltage range is encountered. unlike a microcontroller, which can use an external supervisor device to force the controller into the reset state, a digital potentiometer?s resistance characteristic is not specified. but understanding the operational characteristics can be important in the design of the applications circuit for this low-voltage condition. other application system scenarios where understanding the low-voltage characteristics of the resistor network could be important is for system brown out conditions. for the mcp444x/446x devices, the analog operation is specified at a minimum of 2.7v. device testing has terminal a connected to the device v dd (for the potentiometer configuration only) and terminal b connected to v ss . b.1 low-voltage operation this appendix gives an overview of cmos semiconductor characteristics at lower voltages. this is important so that the 1.8v resistor network characterization graphs of the mcp444x/446x devices can be better understood. for this discussion, we will use the 5 k device data. this data was chosen since the variations of wiper resistance have much greater implications for devices with smaller r ab resistances. figure b-1 shows the worst case r bw error from the average r bw as a percentage, while figure b-2 shows the r bw resistance versus the wiper code graph. non-linear behavior occurs at approximately wiper code 160. this is better shown in figure b-2 , where the r bw resistance changes from a linear slope. this change is due to the change in the wiper resistance. figure b-1: 1.8v worst case r bw error from average r bw (r bw0 -r bw3 ) vs. wiper code and temperature (v dd = 1.8v, i w = 190 a). figure b-2: r bw vs. wiper code and temperature (v dd = 1.8v, i w = 190 a). -7.00% -6.00% -5.00% -4.00% -3.00% -2.00% -1.00% 0.00% 1.00% 2.00% 0 32 64 96 128 160 192 224 256 wiper code error % -40c +25c +85c +125c 0 1000 2000 3000 4000 5000 6000 7000 0 32 64 96 128 160 192 224 256 wiper code resistance () -40c +25c +85c +125c
mcp444x/446x ds22265a-page 92 ? 2010 microchip technology inc. figure b-3 and figure b-4 show the wiper resistance for v dd voltages of 5.5, 3.0, 1.8 volts. these graphs show that as the resistor ladder wiper node voltage (v wcn ) approaches the v dd /2 voltage, the wiper resistance increases. these graphs also show the different resistance characteristics of the nmos and pmos transistors that make up the wiper switch. this is demonstrated by the wiper code resistance curve, which does not mirror itself around the mid-scale code (wiper code = 128). so why are the r w graphs showing the maximum resistance at about mid-scale (wiper code = 128) and the r bw graphs showing the issue at code 160? this requires understanding low-voltage transistor characteristics as well as how the data was measured. figure b-3: wiper resistance (r w ) vs. wiper code and temperature (v dd = 5.5v, i w = 900 a; v dd = 3.0v, i w = 480 a). figure b-4: wiper resistance (r w ) vs. wiper code and temperature (v dd = 1.8v, i w = 260 a). the method in which the data was collected is important to understand. figure b-5 shows the technique that was used to measure the r bw and r w resistance. in this technique, terminal a is floating and terminal b is connected to ground. a fixed current is then forced into the wiper (i w ) and the corresponding wiper voltage (v w ) is measured. forcing a known current through r bw (i w ) and then measuring the voltage difference between the wiper (v w ) and terminal a (v a ), the wiper resistance (r w ) can be calculated, see figure b-5 . changes in i w current will change the wiper voltage (v w ). this may affect the device?s wiper resistance (r w ). figure b-5: r bw and r w measurement. figure b-6 shows a block diagram of the resistor network where the r ab resistor is a series of 256 r s resistors. these resistors are polysilicon devices. each wiper switch is an analog switch made up of an nmos and pmos transistor. a more detailed figure of the wiper switch is shown in figure b-7 . the wiper resistance is influenced by the voltage on the wiper switches nodes (v g , v w and v wcn ). temperature also influences the characteristics of the wiper switch, see figure b-4 . the nmos transistor and pmos transistor have different characteristics. these characteristics, as well as the wiper switch node voltages, determine the r w resistance at each wiper code. the variation of each wiper switch?s characteristics in the resistor network is greater then the variation of the r s resistors. the voltage on the resistor network node (v wcn ) is dependent upon the wiper code selected and the voltages applied to v a , v b and v w . the wiper switch v g voltage to v w or v wcn voltage determines how strongly the transistor is turned on. when the transistor is weakly turned on, the wiper resistance r w will be high. when the transistor is strongly turned on, the wiper resistance (r w ) will be in the typical range. 20 40 60 80 100 120 140 160 180 200 220 0 64 128 192 256 wiper code resistance () -40c @ 3.0v +25c @ 3.0v +85c @ 3.0v +125c @ 3.0v -40c @5.5v +25c @ 5.5v +85c @ 5.5v +125c @ 5.5v 20 520 1020 1520 2020 0 64 128 192 256 wiper code resistance () -40c @ 1.8v +25c @ 1.8v +85c @ 1.8v +125c @ 1.8v a b i v w floating r bw = v w /i w v a v b r w = (v w -v a )/i w
? 2010 microchip technology inc. ds22265a-page 93 mcp444x/446x figure b-6: resistor network block diagram. the characteristics of the wiper are determined by the characteristics of the wiper switch at each of the resistor networks tap points. figure b-7 shows an example of a wiper switch. as the device operational voltage becomes lower, the characteristics of the wiper switch change due to a lower voltage on the v g signal. figure b-7 shows an implementation of a wiper switch. when the transistor is turned off, the switch resistance is in the giga s. when the transistor is turned on, the switch resistance is dependent on the v g , v w and v wcn voltages. this resistance is referred to as r w . figure b-7: wiper switch. so looking at the wiper voltage (v w ) for the 3.0v and 1.8v data gives the graphs in figure b-8 and figure b-9 . in the 1.8v graph, as the v w approaches 0.8v, the voltage increases nonlinearly. since v = i * r, and the current (i w ) is constant, it means that the device resistance increased nonlinearly at around wiper code 160. figure b-8: wiper voltage (v w ) vs. wiper code (v dd = 3.0v, i w = 190 a). figure b-9: wiper voltage (v w ) vs. wiper code (v dd = 1.8v, i w = 190 a). r s a r s r s r s b r w (1) w r w (1) r w (1) r w (1) r w (1) note 1: the wiper resistance is dependent on several factors including, wiper code, device v dd , terminal voltages (on a, b and w), and temperature. r ab nmos pmos n 0 n n-1 n 1 n n n n-2 n n-3 v w v b v a v wc(n-2) dv g note 1: wiper resistance (r w ) depends on the voltages at the wiper switch nodes (v g , v w and v wcn ). r w (1) nmos pmos n wc wiper v g (v dd /v ss ) ?gate? ?gate? v w v wcn 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0 32 64 96 128 160 192 224 256 wiper code wiper voltage (v) -40c +25c +85c +125c 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0 32 64 96 128 160 192 224 256 wiper code wiper voltage (v) -40c +25c +85c +125c
mcp444x/446x ds22265a-page 94 ? 2010 microchip technology inc. using the simulation models of the nmos and pmos devices for the mcp44xx analog switch ( figure b-10 ), we plot the device resistance when the devices are turned on. figure b-11 and figure b-12 show the resistances of the nmos and pmos devices as the v in voltage is increased. the wiper resistance (r w ) is simply the parallel resistance on the nmos and pmos devices (r w = r nmos || r pmos ). below the threshold voltage for the nmos ad pmos devices, the resistance becomes very large (gigaohms). in the transistors active region, the resistance is much lower. for these graphs, the resistances are on different scales. figure b-13 and figure b-14 only plot the nmos and pmos device resistance for their active region and the resulting wiper resistance. for these graphs, all resistances are on the same scale. figure b-10: analog switch. figure b-11: nmos and pmos transistor resistance (r nmos , r pmos ) and wiper resistance (r w ) vs. v in (v dd = 3.0v). figure b-12: nmos and pmos transistor resistance (r nmos , r pmos ) and wiper resistance (r w ) vs. v in (v dd = 1.8v). figure b-13: nmos and pmos transistor resistance (r nmos , r pmos ) and wiper resistance (r w ) vs. v in (v dd = 3.0v). figure b-14: nmos and pmos transistor resistance (r nmos , r pmos ) and wiper resistance (r w ) vs. v in (v dd = 1.8v). r w nmos pmos v g (v dd /v ss ) ?gate? ?gate? v out v in 0.00e+00 5.00e+09 1.00e+10 1.50e+10 2.00e+10 2.50e+10 3.00e+10 0.0 0.3 0.6 0.9 1.2 1.5 1.8 v in voltage nmos and pmos resistance () 0 500 1000 1500 2000 2500 wiper resistance () r pmos r nmos r w pmos theshold nmos theshold 0.00e+00 1.00e+09 2.00e+09 3.00e+09 4.00e+09 5.00e+09 6.00e+09 7.00e+09 0.0 0.6 1.2 1.8 2.4 3.0 v in voltage nmos and pmos resistance () 0 20 40 60 80 100 120 140 160 wiper resistance () r pmos r nmos r w pmos theshold nmos theshold 0 50 100 150 200 250 300 0.0 0.6 1.2 1.8 2.4 3.0 v in voltage resistance () r pmos r nmos r w 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 0.0 0.3 0.6 0.9 1.2 1.5 1.8 v in voltage resistance () r pmos r nmos r w
? 2010 microchip technology inc. ds22265a-page 95 mcp444x/446x b.2 optimizing circuit design for low-voltage characteristics the low-voltage nonlinear characteristics can be minimized by application design. the section will show two application circuits that can be used to control a programmable reference voltage (v out ). minimizing the low-voltage nonlinear characteristics is done by keeping the voltages on the wiper switch nodes at a voltage where either the nmos or pmos transistor is turned on. an example of this is if we are using a digital potentiometer for a voltage reference (v out ). let?s say that we want v out to range from 0.5 * v dd to 0.6 * v dd . in example implementation #1 ( figure b-15 ), we window the digital potentiometer using resistors r1 and r2. when the wiper code is at full scale, the v out voltage will be 0.6 * v dd, and when the wiper code is at zero scale the v out voltage will be 0.5 * v dd . remember that the digital potentiometers r ab variation must be included. ta b l e b - 1 shows that the v out voltage can be selected to be between 0.455 * v dd and 0.727 * v dd , which includes the desired range. with respect to the voltages on the resistor network node, at 1.8v the v a voltage would range from 1.29v to 1.31v while the v b voltage would range from 0.82v to 0.86v. these voltages cause the wiper resistance to be in the nonlinear region (see figure b-12 ). in potentiometer mode, the variation of the wiper resistance is typically not an issue, as shown by the inl/dnl graph ( figure 2-7 ). in example implementation #2 ( figure b-16 ) we use the digital potentiometer in rheostat mode. the resistor ladder uses resistors r1 and r2 with r bw at the bottom of the ladder. when the wiper code is at full scale, the v out voltage will be 0.6 * v dd and when the wiper code is at full scale the v out voltage will be 0.5 * v dd . remember that the digital potentiometers r ab variation must be included. ta b l e b - 2 shows that the v out voltage can be selected to be between 0.50 * v dd and 0.687 * v dd , which includes the desired range. with respect to the voltages on the resistor network node, at 1.8v the v w voltage would range from 0.29v to 0.38v. these voltages cause the wiper resistance to be in the linear region (see figure b-12 ). figure b-15: example implementation #1. table b-1: example #1 voltage calculations variation min typ max r1 12,000 12,000 12,000 r2 20,000 20,000 20,000 r ab 8,000 10,000 12,000 v out (@ fs) 0.714 v dd 0.70 v dd 0.727 v dd v out (@ zs) 0.476 v dd 0.50 v dd 0.455 v dd v a 0.714 v dd 0.70 v dd 0.727 v dd v b 0.476 v dd 0.50 v dd 0.455 v dd legend: fs ? full scale, zs ? zero scale a b w v w v a v b r1 r2 v out
mcp444x/446x ds22265a-page 96 ? 2010 microchip technology inc. figure b-16: example implementation #2. table b-2: example #2 voltage calculations variation min typ max r1 10,000 10,000 10,000 r2 10,000 10,000 10,000 r bw (max) 8,000 10,000 12,000 v out (@ fs) 0.667 v dd 0.643 v dd 0.687 v dd v out (@ zs) 0.50 v dd 0.50 v dd 0.50 v dd v w (@ fs) 0.333 v dd 0.286 v dd 0.375 v dd v w (@ zs) v ss v ss v ss legend: fs ? full scale, zs ? zero scale a b w v w v a r1 r2 v out v b
? 2010 microchip technology inc. ds22265a-page 97 mcp444x/446x product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . part no. x /xx -xxx resistance package temperature range device device mcp4441: quad nonvolatile 7-bit potentiometer mcp4441t: quad nonvolatile 7-bit potentiometer (tape and reel) mcp4442: quad nonvolatile 7-bit rheostat mcp4442t: quad nonvolatile 7-bit rheostat (tape and reel) mcp4461: quad nonvolatile 8-bit potentiometer mcp4461t: quad nonvolatile 8-bit potentiometer (tape and reel) mcp4462: quad nonvolatile 8-bit rheostat mcp4462t: quad nonvolatile 8-bit rheostat (tape and reel) resistance version: 502 = 5 k 103 = 10 k 503 = 50 k 104 = 100 k temperature range e = -40 c to +125 c (extended) package st = plastic thin shrink small outline (tssop), 14/20-lead ml = plastic quad flat no-lead (4x4 qfn), 20-lead examples: a) mcp4441-502e/xx: 5 k , 20-ld device b) mcp4441t-502e/xx: t/r, 5 k , 20-ld device c) mcp4441-103e/xx: 10 k , 20-ld device d) mcp4441t-103e/xx: t/r, 10 k , 20-ld device e) mcp4441-503e/xx: 50 k , 20-ld device f) mcp4441t-503e/xx: t/r, 50 k , 20-ld device g) mcp4441-104e/xx: 100 k , 20-ld device h) mcp4441t-104e/xx: t/r, 100 k , 20-ld device a) mcp4442-502e/xx: 5 k , 14-ld device b) mcp4442t-502e/xx: t/r, 5 k , 14-ld device c) mcp4442-103e/xx: 10 k , 14-ld device d) mcp4442t-103e/xx: t/r, 10 k , 14-ld device e) mcp4442-503e/xx: 50 k , 8ld device f) mcp4442t-503e/xx: t/r, 50 k , 14-ld device g) mcp4442-104e/xx: 100 k , 14-ld device h) mcp4442t-104e/xx: t/r, 100 k , 14-ld device a) mcp4461-502e/xx: 5 k , 20-ld device b) mcp4461t-502e/xx: t/r, 5 k , 20-ld device c) mcp4461-103e/xx: 10 k , 20-ld device d) mcp4461t-103e/xx: t/r, 10 k , 20-ld device e) mcp4461-503e/xx: 50 k , 20-ld device f) mcp4461t-503e/xx: t/r, 50 k , 20-ld device g) mcp4461-104e/xx: 100 k , 20-ld device h) mcp4461t-104e/xx: t/r, 100 k , 20-ld device a) mcp4462-502e/xx: 5 k , 14-ld device b) mcp4462t-502e/xx: t/r, 5 k , 14-ld device c) mcp4462-103e/xx: 10 k , 14-ld device d) mcp4462t-103e/xx: t/r, 10 k , 14-ld device e) mcp4462-503e/xx: 50 k , 14-ld device f) mcp4462t-503e/xx: t/r, 50 k , 14-ld device g) mcp4462-104e/xx: 100 k , 14-ld device h) mcp4462t-104e/xx: t/r, 100 k , 14-ld device xx = st for 14/20-lead tssop = ml for 20-lead qfn version
mcp444x/446x ds22265a-page 98 ? 2010 microchip technology inc. notes:
? 2010 microchip technology inc. ds22265a-page 99 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mxdev, mxlab, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, appl ication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, octopus, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, total endurance, tsharc, uniwindriver, wiperlock and zena are trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2010, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-1-60932-533-6 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
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